Datasheet

6
MSL2021 [DATASHEET]
42062A–LED–02/2013
5. The maximum SDA and SCL rise times is 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be connected between SDA
and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time.
6. Includes input filters on SDA and SCL that suppress noise less than 50ns.
7. Additional decoupling may be required when pulling current from VCC and/or VDD in noisy environments.
8. 2µs minimum on time for main LED string PWM dimming.
Typical Operating Characteristics
Figure 5-1. Start-up behavior, PWM = 10% duty cycle (Test conditions).
Figure 5-2. Start-up behavior, PWM = 90% duty cycle (Test conditions).
V
LED
I
in
I
main
FBO
V
LED
I
in
I
main
FBO