Datasheet

5
MSL2021 [DATASHEET]
42062A–LED–02/2013
Table 5-2. AC electrical characteristics
Table 5-3. I
2
C switching characteristics
Notes: 1. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface when either SDA or SCL is held low for t
TIMEOUT
.
2. SDA Data Valid Acknowledge Time is SCL LOW to SDA (out) LOW acknowledge time.
3. SDA Data Valid Time is minimum SDA output data-valid time following SCL LOW transition.
4. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state.
FBO LSB Current 1.0 A
THM Source Current 100 A
THM Voltage Range 0 1.5 V
Thermal Shutdown Temperature
Temperature rising
133 °C
Thermal Shutdown Hysteresis 15 °C
Parameter Conditions Min. Typ. Max. Unit
DRV t
OFF
timing
R
TOFF
= 45.3k
0.5 s
PWM Input Frequency
(8)
60 10,000 Hz
PWM Duty Cycle 1 100 %
PWM Duty Cycle Resolution
MSL2021
0.4 %
Parameter Symbol Conditions Min. Typ. Max. Unit
SCL Clock Frequency
(1)
0.05 1,000 kHz
STOP to START Condition Bus Free
Time
t
BUF
0.5 µs
Repeated START condition Hold Time t
HD:STA
0.26 µs
Repeated START condition Setup Time t
SU:STA
0.26 µs
STOP Condition Setup Time t
SU:STOP
0.26 µs
SDA Data Hold Time t
HD:DAT
5 ns
SDA Data Valid Acknowledge Time
(2)
0.05 0.55 µs
SDA Data Valid Time
(3)
0.05 0.55 µs
SDA Data Set-Up Time t
SU:DAT
100 ns
SCL Clock Low Period t
LOW
0.5 µs
SCL Clock High Period t
HIGH
0.26 µs
SDA, SCL Fall Time t
F
(4)(5)
120 ns
SDA, SCL Rise Time
t
R
120 ns
SDA, SCL Input Suppression Filter
Period
(6)
50 ns
Bus Timeout
t
TIMEOUT
(1)
25 ms
Parameter Conditions Min. Typ. Max. Unit