Datasheet

32
MSL2021 [DATASHEET]
42062A–LED–02/2013
Figure 14-1. I
2
C Interface Connections
A transmission consists of a START condition sent by a master, a 7-bit slave address plus one R/W bit, an acknowledge
bit, none or many data bytes each separated by an acknowledge bit, and a STOP condition (Figure 14-2, Figure 14-4 and
Figure 14-5 on page 33).
Figure 14-2. I
2
C Serial Interface Timing Details
14.1 I
2
C Bus Timeout
The bus timeout feature allows the MSL2021 to reset the serial bus interface if a communication ceases before a STOP
condition is sent. If SCL or SDA is low for more than 25ms (typical), then the MSL2021 terminates the transaction,
releases SDA and waits for another START condition.
14.2 I
2
C Bit Transfer
One data bit is transferred during each clock pulse. SDA must remain stable while SCL is high.
Figure 14-3. I
2
C Bit Transfer
MASTER
(µC)
SDA
INT
SCL
SDA
FLTB
SCL
MSL2021
V
I2C
2 x 2.2k
TYPICAL
100k
START
CONDITION
REPEATED START
CONDITION
STAR
T
CONDITION
STOP
CONDITION
t
HD:ST
A
t
R
t
F
t
HIGH
t
LOW
t
SU:DAT
t
HD:DAT
t
SU:ST
A
t
HD :ST
A
t
SU:STO
t
BUF
SD
A
SCL
SD
A
SCL
SDA LEVEL STABLE
SDA DATA VALID
SDA ALLOWED TO
CHANGE LEVEL