Datasheet

23
Atmel MSL2010 [DATASHEET]
42072A–AVR–05/2013
15.4 I
2
C Acknowledge Bit
The acknowledge bit is a clocked 9th bit which the recipient uses to handshake receipt of each byte of data. The master
generates the 9th clock pulse, and the recipient holds SDA low during the high period of the clock pulse. When the
master is transmitting to the MSL2010, the MSL2010 pulls SDA low because the MSL2010 is the recipient. When the
MSL2010 is transmitting to the master, the master pulls SDA low because the master is the recipient.
Figure 15-5. I
2
C Acknowledge
15.5 I
2
C Slave Address
The MSL2021 has a 7-bit long slave address, 0b0100000, followed by an eighth bit, the R/W bit. The R/W bit is low for a
write to the MSL2010, high for a read from the MSL2010. All MSL2010 devices have the same slave address; when
using multiple devices and communicating with them through their serial interfaces, make external provision to route the
serial interface to the appropriate device. Note that development systems that use I
2
C often left-shift the address one
position before they insert the R/W bit, and thus expect a base address setting of 0x20 instead of 0x40.
Figure 15-6. I
2
C Slave Address
15.6 I
2
C Message Format for Writing to the MSL2010
A write to the MSL2010 contains the MSL2010’s slave address, the R/W bit cleared to 0, and at least 1 byte of
information (Figure 15-7 on page 24). The first byte of information is the register address byte. The register address byte
is stored as a register pointer, and determines which register the following byte is written into. If a STOP condition is
detected after the register address byte is received, then the MSL2010 takes no further action beyond setting the register
pointer.
SDA
TRANSMITTER
SCL
START
CONDITION
ACKNOWLEDGE
BY RECEIVER
S A
SDA
RECEIVER
12 891
SDA
SCL
1 2 3 4 5 6 7 8 9
A7 = 0 AA6 = 1 A5 = 0
A4 = 0 A3 =0 A2 = 0 A1 = 0 R / W
MSB