Datasheet

22
Atmel MSL2010 [DATASHEET]
42072A–AVR–05/2013
Figure 15-2. I
2
C Serial Interface Timing Details
15.1 I
2
C Bus Timeout
The bus timeout feature allows the MSL2010 to reset the serial bus interface if a communication ceases before a STOP
condition is sent. If SCL or SDA is low for more than 25ms (typical), then the MSL2010 terminates the transaction,
releases SDA and waits for another START condition.
15.2 I
2
C Bit Transfer
One data bit is transferred during each clock pulse. SDA must remain stable while SCL is high.
Figure 15-3. I
2
C Bit Transfer
15.3 I
2
C START and STOP Conditions
Both SCL and SDA remain high when the interface is free. The master signals a transmission with a START condition (S)
by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it
issues a STOP condition (P) by transitioning SDA from low to high while SCL is high. The bus is then free.
Figure 15-4. I
2
C START and STOP Conditions
START
CONDITION
REPEATED START
CONDITION
STAR
T
CONDITION
STOP
CONDITION
t
HD:ST
A
t
R
t
F
t
HIGH
t
LOW
t
SU:DAT
t
HD:DAT
t
SU:ST
A
t
HD :ST
A
t
SU:STO
t
BUF
SD
A
SCL
SD
A
SCL
SDA LEVEL STABLE
SDA DATA VALID
SDA ALLOWED TO
CHANGE LEVEL
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P