Datasheet

MRF49XA
DS70590C-page 84 Preliminary © 2009-2011 Microchip Technology Inc.
5.1 Timing Specification and Diagram
FIGURE 5-1: SPI TIMING DIAGRAM
TABLE 5-8: SPI TIMING SPECIFICATION
Symbol Parameter Minimum Value (ns)
t
CH
Clock High Time 25
t
CL
Clock Low Time 25
t
SS
Select Setup Time (CS falling edge to SCK rising edge) 10
t
SH
Select Hold Time (SCK falling edge to CS rising edge) 10
t
SHI
Select High Time 25
t
DS
Data Setup Time (SDI transition to SCK rising edge) 5
t
DH
Data Hold Time (SCK rising edge to SDI transition) 5
t
OD
Data Delay Time 10
t
CH
t
SS
t
CL
t
SHI
t
DS
t
DH
t
CD
SCK
SDI
SDO
BIT 15
TXRXFIFO
BIT 14 BIT 8BIT 13 BIT 7 BIT 1 BIT 0
POR
TXOWRXOF
OFFSB(0)DQDO FIFO OUT
t
SH
CS
ATRSSI