Datasheet

© 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 67
MRF49XA
FIGURE 3-15: TX REGISTER BLOCK DIAGRAM (DURING TRANSMIT)
8-Bit Shift Register
SCLK
Serial Bus Data
CLK
SDI
CLK
SDI
SDO
SDO
TX_DATA
MUX
SEL
11
10
Y
SEL
11
10
Y
SEL
11
10
Y
MUX
MUX
TXCEN = 1
(During TX)
8-Bit Shift Register
1:8
Bit Rate
Divider
Note: The data registers’ content is initialized by clearing the TXCEN bit.