Datasheet

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MRF49XA

FIGURE 3-3: SENSITIVE RESET DISABLED

3.1.3 SOFTWARE RESET

The Software Reset is initiated using the host

microcontroller. The 0xFE00 command triggers this

Reset only if the Sensitive Reset mode is enabled. The

hardware automatically clears the bit(s) to their

power-on state. The Software Reset command is the

same as POR, but the duration of the Reset event is

much less than the actual POR (0.25 ms, typical).

3.1.4 RESET PIN

The MRF49XA has an open-drain Reset output with an

internal pull-up and input buffer (active-low). The host

microcontroller resets the MRF49XA by asserting the

RESET

pin to low (see Figure 3-4). All control registers

are reset to their POR values. The RESET

pin consists

of an internal weak pull-up resistor. In order to allow the

RF circuitry to start-up and get stabilized, a delay of

around 0.25 ms is recommended for accessing the

MRF49XA after a hardware Reset.

FIGURE 3-4: RESET PIN INTERNAL

CONNECTION

The registers associated with Reset are:

•STSREG (see Register 2-1)

• FIFORSTREG (see Register 2-10)

• WTSREG (see Register 2-14)

250 mV

Reset Threshold

Voltage (600 mV)

Reset Ramp Line

(100 mV/ms)

Time

VDD

RESET

Output

(Pin 10)

RESET

VDD

100k

10k

To Internal

Reset Logic

From POR

Circuit

To MCU Reset

(Input/Output*)

* These pins can be left floating.