Datasheet

MRF49XA
DS70590C-page 44 Preliminary © 2009-2011 Microchip Technology Inc.
3.1.2 POWER GLITCH RESET
Spikes or glitches are found on the VDD line if the power
supply filtering is not satisfactory, or the internal
resistance of the power supply is very high. So, in this
case, the Sensitive Reset mode needs to be enabled.
Here, the device Reset occurs due to the transients
present on the V
DD line.
The internal Reset block has two basic modes of
operation:
• Sensitive Reset mode
• Normal Reset mode
Sensitive Reset mode: Enabling the Sensitive Reset,
a Reset is generated if:
• the positive going edge of the V
DD has a rising
rate greater than 100 mV/ms, and
• the voltage difference between the internal ramp
signal and the V
DD reaches the Reset threshold
voltage (600 mV).
The Sensitive Reset mode is the default mode which
can be changed using the DRSTM bit
(FIFORSTREG<0>). Figure 3-2 shows the Sensitive
Reset mode.
Normal Reset mode: The device enters this mode,
when the power glitch detection circuit is disabled.
Figure 3-3 shows the Normal Reset mode.
If the Sensitive mode is disabled and the power supply
is turned off, the V
DD requires 250 mV to trigger a
Power-on Reset when the supply voltage is reapplied.
If the decoupling capacitors retain their charges for a
longer duration, there might be no Reset after
power-up as the power glitch detector is disabled.
FIGURE 3-2: SENSITIVE RESET ENABLED
Note: Negative change in the supply voltage does
not cause a Reset event unless the V
DD
level reaches the Reset threshold voltage
(i.e., 250 mV in Normal Reset mode, 1.6V in
Sensitive Reset mode).
Note: The Reset event reinitializes the internal
registers, and thus, the Sensitive mode is
enabled again.
VDD
1.6V
H
L
Reset Threshold
Voltage (600 mV)
Reset Ramp Line
(100 mV/ms)
Time
RESET
Output
(Pin 10)