Datasheet

MRF49XA

EQUATION 2-4:

EQUATION 2-5:

EQUATION 2-6:

W-1 W-1 W-0 W-0 W-0 W-1 W-1 W-0

CCB<15:8>

bit 15 bit 8

W-0 W-0 W-1 W-0 W-0 W-0 W-1 W-1

DRPE DRPV<6:0>

(1)

bit 7 bit 0

Legend: r = reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 CCB<15:8>: Command Code bits

The command code bits (11000110b) are serially sent to the microcontroller to identify the bits to be

written in the DRSREG.

bit 7 DRPE: Date Rate Prescaler Enable bit

1 = Enables the prescaler to obtain smaller values of expected data rates. The prescaler value when

enabled is approximately 1/8 of the actual data rate.

0 = Disables the prescaler

bit 6-0 DRPV<6:0>: Data Rate Parameter Value bits

(1)

These bits represent the decimal value of the 7-bit parameter which is used to calculate the expected

data rate.

Note 1: To calculate the expected data rate, use Equation 2-4. To calculate the DRPV<6:0> decimal value for a given

bit rate, use Equation 2-5. If the prescaler is not used, the data rates range from 2.694 kbps–344.828 kbps.

With the prescaler enabled, the data rates range from 337 bps to 43.103 kbps. The Slow Clock Recovery

mode requires more accurate bit timing when setting the data rate. Equation 2-6 is used to calculate the data

rate accuracy for Fast and Slow modes.

DREx (kbps) = 10000/[29 x (DRPV<6:0> + 1) x (1 + DRPE x 7)]

where:

DRPV<6:0> is the Decimal Value from 0 to 127 and the Prescaler (DRPE) is ‘1’ (if ON) or ‘0’ (if OFF).

DRPV<6:0> = 10000/[29 x (1 + DRPE x 7) x DREx] – 1

where:

DREx is the Expected Data Rate.

• Slow mode Accuracy (SMA) = ΔDR/DR < 1/(29 x LN)

• Fast mode Accuracy (FMA) = ΔDR/DR < 3/(29 x LN)

where:

LN is the longest number of expected 1’s or 0’s in the data stream.

ΔDR is the difference in the actual data rate versus the set data rate in the transmitter.

DR is the expected data rate set using DRPV<6:0>.