Datasheet
© 2009-2011 Microchip Technology Inc. Preliminary DS70590C-page 33
MRF49XA
TABLE 2-8: SYNCHRONOUS CHARACTER SELECTION
SYCHLEN SCL1 SCL0 Synchronous Character
1 NA 0xD4 0xD4 (byte long)
0 0x2D 0xD4 0x2DD4 (word long)
TABLE 2-9: RESET MODE SELECTION
DRSTM Reset mode Condition
1 Normal Reset Reset is triggered when V
DD is below 250 mV
0 Sensitive Reset Reset is triggered when VDD is below 1.6V and VDD glitch
is greater than 600 mV
Note: See Appendix A: “Read Sequence and Packet Structures” for FIFO packet structures.