Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsDev KitsPCB design board

MRF49XA

W-1 W-0 W-0 W-0 W-0 W-0 W-0 W-0

CCB<15:8>

bit 15 bit 8

W-0 W-0 W-0 W-0 W-1 W-0 W-0 W-0

TXDEN FIFOEN FBS<1:0> LCS<3:0>

bit 7 bit 0

Legend: r = reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 CCB<15:8>: Command Code bits

The command code bits (10000000b) are serially sent to the microcontroller to identify the bits to be

written in the GENCREG.

bit 7 TXDEN: TX Data Register Enable bit

1 = Internal TX Data register enabled

(1)

0 = Internal TX Data register disabled; no transmit

bit 6 FIFOEN: FIFO Enable bit

1 = Internal data FIFO enabled; the FIFO is used to store data during receive

(2)

0 = FIFO disabled; FSK/DATA/FSEL and RCLKOUT/FCAP/FINT are used to receive data

bit 5-4 FBS<1:0>: Frequency Band Select bits

These bits set the frequency band to be used in Sub-GHz range.

11 = 915 MHz

10 = 868 MHz

01 = 433 MHz

00 = Reserved

bit 3-0 LCS<3:0>: Load Capacitance Select bits

These bits set and vary the internal load capacitance for the crystal reference.

1111 = 16.0 pF

1110 = 15.5 pF

1101 = 15.0 pF

1100 = 14.5 pF

1011 = 14.0 pF

1010 = 13.5 pF

1001 = 13.0 pF

1000 = 12.5 pF

0111 = 12.0 pF

0110 = 11.5 pF

0101 = 11.0 pF

0100 = 10.5 pF

0011 = 10.0 pF

0010 = 9.5 pF

0001 = 9.0 pF

0000 = 8.5 pF

Note 1: If the internal TX data register is used, the DATA/FSK/FSEL

pin must be pulled “high”.

2: If the data FIFO is used, the DATA/FSK/FSEL

pin must be pulled “low”.