Datasheet

MRF49XA
DS70590C-page 18 Preliminary © 2009-2011 Microchip Technology Inc.
2.16 Memory Organization
The memory in MRF49XA is implemented as static
RAM and is accessible through the SPI port. Each
memory location functionally addresses a register, con-
trol, status or data/FIFO fields, as shown in Table 2-10.
The command/control registers provide control, status
and device address for transceiver operations. The
FIFOs serve as temporary buffers for data transmission
and reception.
The commands to the device are sent serially. All
17 commands basically address the 17 registers
affiliated to it. The registers consist of a command
code, followed by control, data, status or parameter
bits. The MSb is sent first in all of the commands (e.g.,
bit 15 for a 16-bit command). The POR circuit sets the
default values in all control and command registers.
In general, MRF49XA registers are read only. Hence
the chip status can only be read by the Status Read
Register. During write, only appropriate byte is written
to the desired register. It is not desired to read/write all
registers and there is no way to read back the register.
TABLE 2-4: CONTROL (COMMAND) REGISTER DESCRIPTION
SI. No. Register Name Register Description Related Control Functions
1 STSREG Status Read Register Receive register/FIFO, transmit register,
interrupt, frequency control and signal
strength, POR, wake-up timer, low battery
detect, data quality, clock recovery
2 GENCREG General Configuration Register Frequency band select, enables TX and RX
registers, crystal load capacitor bank value
3 AFCCREG AFC Configuration Register AFC locking range, mode, accuracy and
enable
4 TXCREG Transmit Configuration Register Modulation polarity, modulation bandwidth,
transmit power and deviation
5 TXBREG Transmit Byte Register Transmit data byte
6 CFSREG Center Frequency Value Set Register Transmit or receive frequency
7 RXCREG Receive Control Register Function of pin 16, DIO mode, RX BBBW,
LNA gain, digital RSSI threshold
8 BBFCREG Baseband Filter Configuration Register Clock Recovery mode, data indicator
parameter value and filter type
9 RXFIFOREG Receiver FIFO Read Register Receive data byte
10 FIFORSTREG FIFO and Reset mode Configuration
Register
FIFO interrupt level, FIFO start control and
FIFO enable, POR Sensitivity mode,
synchronous character length
11 SYNBREG Synchronous Byte Configuration Register Synchronous character pattern
12 DRSREG Data Rate Value Set Register Data rate prescalar set
13 PMCREG Power Management Configuration Register Enables receive and transmit chain,
baseband circuit, synthesizer circuit,
oscillator, wake-up timer, low battery detect
and clock out
14 WTSREG Wake-up Timer Value Set Register Wake-up timer values for time interval
15 DCSREG Duty Cycle Value Set Register Duty Cycle mode and value
16 BCSREG Battery Threshold Detect and Clock Output
Value Set Register
Low battery detect threshold values and
clock output frequency
17 PLLCREG PLL Configuration Register Clock out buffer speed, PLL bandwidth,
dithering and delay