Datasheet

MRF49XA DS70590C-page 10 Preliminary © 2009-2011 Microchip Technology Inc.
FIGURE 2-1: MRF49XA ARCHITECTURAL BLOCK DIAGRAM
8
PA/LNA and PLL/CLK
Block
Baseband Amplifier/Filter/Limiter
Block
Low-Power Block
Microcontroller Interface Block
Power
Supply Block
Data Processing Block
AFCDQI
Comparator
FIFO
Data Filtering
and Clock
Recovery Unit
I/Q
DEMOD
LBDB
WUTM
with
calibration
OSCCLK
RSSI
1 32 4 105 16 14119 15
Self Calibration
PLL and I/Q VCO with
Calibration
MIX
MIX
12
13
6
7
CLK
DATA
SDI SCK SDO
FSK/DATA/
FSEL
RCLKOUT/
FCAP/FINT
CLKOUT RSSIO V
DDVSS
RFP
RFN
RFXTL/
EXTREF
I
Q
____
Clock Block
LNA
PA
AMP
Cal
Ckt
AMP
Cal
Ckt
IRO
CS
__
INT/DIO
RESET