MRF49XA Data Sheet ISM Band Sub-GHz RF Transceiver © 2009-2011 Microchip Technology Inc.
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MRF49XA ISM Band Sub-GHz RF Transceiver Features Baseband Features • Fully Integrated Sub-GHz Transceiver • Supports Proprietary Sub-GHz Wireless Protocols • 4-Wire Serial Peripheral Interface (SPI) Compatible Interface • CMOS/TTL Compatible I/Os • Clock and Reset Signals for Microcontroller • Integrated 10 MHz Oscillator Circuitry • Integrated Low Battery Voltage Detector • Supports Power-Saving modes • Operating Voltage: 2.2V–3.
MRF49XA Pin Diagram: 16-Pin TSSOP DS70590C-page 4 SDI 1 16 INT/DIO SCK 2 15 RSSIO CS 3 14 VDD SDO 4 13 RFN MRF49XA IRQ 5 12 RFP FSK/DATA/FSEL 6 11 VSS RCLKOUT/FCAP/FINT 7 10 RESET CLKOUT 8 9 Preliminary RFXTL/EXTREF © 2009-2011 Microchip Technology Inc.
MRF49XA Table of Contents 1.0 Introduction................................................................................................................................................................................... 7 2.0 Hardware Description................................................................................................................................................................... 9 3.0 Functional Description........................................................................
MRF49XA NOTES: DS70590C-page 6 Preliminary © 2009-2011 Microchip Technology Inc.
MRF49XA 1.0 INTRODUCTION Microchip’s MRF49XA is a fully integrated Sub-GHz RF transceiver.
MRF49XA FIGURE 1-1: FUNCTIONAL NODE BLOCK DIAGRAM Antenna MRF49XA RF Block Matching Circuitry RFP PA/LNA and PLL/CLK Block RFN Baseband Amplifier/ Filter/ Limiter SPI Signals Data Processing Unit MCU Interface Other Handshaking Signals Power Management Memory 10 MHz FIGURE 1-2: MICROCONTROLLER TO MRF49XA INTERFACE PIC® MCU MRF49XA I/O/SS IRO __ CS SDO SDI SDI SDO SCK SCK INT I/O INT/DIO* I/O RESET* I/O FSK/DATA/FSEL* CLKOUT* OSC1 I/O RCLKOUT/FCAP/FINT* * Implies optional si
MRF49XA 2.0 HARDWARE DESCRIPTION The MRF49XA is an integrated, single chip ISM Band Sub-GHz Transceiver. A simplified architectural block diagram of the MRF49XA is shown in Figure 2-1. The frequency synthesizer is clocked by an external 10 MHz crystal and generates the 433, 868 and 915 MHz radio frequency. The receiver with a Zero-IF architecture consists of the following components: • • • • • The quality of the data is checked or validated using the RSSI and DQI blocks built into the transceiver.
MRF49XA ARCHITECTURAL BLOCK DIAGRAM MIX I Cal AMP Ckt LNA RFN 13 RFP 12 7 Self Calibration MIX Q Data Filtering and Clock Recovery Unit I/Q DEMOD CLK DATA 6 Cal AMP Ckt FIFO PA Preliminary PLL and I/Q VCO with Calibration PA/LNA and PLL/CLK Block CLK OSC © 2009-2011 Microchip Technology Inc.
MRF49XA TABLE 2-1: Pin PIN DESCRIPTION Symbol Type 1 SDI Digital Input Serial data input interface to MRF49XA (SPI input signal). 2 SCK Digital Input Serial clock interface (SPI clock). 3 CS Digital Input Serial interface chip select (SPI chip/device select). 4 SDO Digital Output Serial data output interface from MRF49XA (SPI output signal).
MRF49XA TABLE 2-1: PIN DESCRIPTION (CONTINUED) Pin Symbol Type Description 9 RFXTL/EXTREF Analog Input RF Crystal: This pin is connected to a 10 MHz series crystal or to an external oscillator reference. The crystal is used as a reference for the PLL which generates the local oscillator frequency. It is possible to “pull” the crystal to the accurate frequency by changing the load capacitor value.
MRF49XA 2.1 Power and Ground Pins The power supply bypassing is very essential for better handling of signal surges and noise in the power line. The large value decoupling capacitors should be placed at the PCB power input. The smaller value decoupling capacitors should be placed at every power point of the device and at bias points for the RF port.
MRF49XA 2.5 RFXTL/EXTREF and CLKOUT Pins The MRF49XA has an internal, integrated crystal oscillator circuit, and therefore, a single RFXTL/EXTREF pin is used as a crystal oscillator. The crystal oscillator circuit, with internal loading capacitors, provides a 10 MHz reference signal for the PLL. The PLL, in turn, generates the local oscillator frequency. It is possible to “pull” the crystal to the accurate frequency by changing the load capacitor value.
MRF49XA 2.10 2.10.1 Data Validity Blocks 2.10.2 RECEIVE SIGNAL STRENGTH INDICATOR The MRF49XA provides the RSSI signal to the host microcontroller, and hence, supports the monitoring of analog and digital signal strengths. A digital RSSI output is provided to monitor the input signal level through an internal STATUS register. The digital RSSI goes high, if the received signal strength exceeds a given preprogrammed RSSI threshold level. The digital RSSI can be monitored by reading the STSREG.
MRF49XA 2.11 2.11.1 Power-Saving Blocks 2.12 LOW BATTERY VOLTAGE DETECTOR The integrated low-battery voltage detector circuit monitors the supply voltage against a preprogrammed value and generates an interrupt on the IRO pin if it falls below the programmed threshold level. The detector circuit has a built-in 50 mV hysteresis. 2.11.2 WAKE-UP TIMER The current consumption of the programmable wake-up timer is very low, typically 1.5 μA.
MRF49XA 2.14 Receive FIFO The received data in MRF49XA is filled into a 16-bit First In First Out (FIFO) register. The FIFO is configured to generate an interrupt after receiving a defined number of bits. When the internal FIFO is enabled, the FIFO interrupt pin (RCLKOUT/FCAP/FINT) acts as a FIFO full interrupt, indicating that the FIFO has been filled to its preprogrammed limit.
MRF49XA 2.16 Memory Organization The memory in MRF49XA is implemented as static RAM and is accessible through the SPI port. Each memory location functionally addresses a register, control, status or data/FIFO fields, as shown in Table 2-10. The command/control registers provide control, status and device address for transceiver operations. The FIFOs serve as temporary buffers for data transmission and reception. code, followed by control, data, status or parameter bits.
MRF49XA 2.
MRF49XA REGISTER 2-1: STSREG: STATUS READ REGISTER (POR: 0x0000)(1) (CONTINUED) bit 10 LBTD: Low Battery Threshold Detect bit Indicates whether the battery or supply voltage is below the preprogrammed threshold limit. 1 = Supply voltage is below threshold 0 = Normal supply voltage feed bit 9 FIFOEM: FIFO Empty bit Indicates whether the receive FIFO is empty or filled.
MRF49XA REGISTER 2-2: GENCREG: GENERAL CONFIGURATION REGISTER (POR: 0x8008) W-1 W-0 W-0 W-0 W-0 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 TXDEN FIFOEN W-0 W-0 W-1 W-0 FBS<1:0> W-0 W-0 LCS<3:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (10000000b) are serially sent to the micr
MRF49XA REGISTER 2-3: W-1 AFCCREG: AUTOMATIC FREQUENCY CONTROL CONFIGURATION REGISTER (POR: 0xC4F7) W-1 W-0 W-0 W-0 W-1 W-0 W-0 CCB<15:8> bit 15 bit 8 W-1 W-1 AUTOMS<1:0> W-1 W-1 ARFO<1:0> W-0 W-1 W-1 W-1 MFCS HAM FOREN FOFEN bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000100
MRF49XA REGISTER 2-4: W-1 TXCREG: TRANSMIT CONFIGURATION REGISTER (POR: 0x9800) W-0 W-0 W-1 W-1 W-0 W-0 W-0 CCB<15:9> MODPLY bit 15 bit 8 W-0 W-0 W-0 MODBW<3:0> W-0 W-0 r W-0 W-0 W-0 OTXPWR<2:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 CCB<15:9>: Command Code bits The command code bits (1001100b) are serially sent to the microc
MRF49XA REGISTER 2-4: TXCREG: TRANSMIT CONFIGURATION REGISTER (POR: 0x9800) (CONTINUED) OTXPWR<2:0>: Output Transmit Power Range bits(2) These bits set the transmit output power range. The output power is programmable from 0 dB (Max.) to -17.5 dB in -2.5 dB steps. 111 = -17.5 dB 110 = -15.0 dB 101 = -12.5 dB 100 = -10.5 dB 011 = -7.5 dB 010 = -5.0 dB 001 = -2.
MRF49XA REGISTER 2-5: W-1 TXBREG: TRANSMIT BYTE REGISTER (POR: 0xB8AA) W-0 W-1 W-1 W-1 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-1 W-0 W-1 W-0 W-1 W-0 W-1 W-0 TXDB<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (10111000b) are serially sent to the microcontroller to identify the bits to
MRF49XA REGISTER 2-6: CFSREG: CENTER FREQUENCY VALUE SET REGISTER (POR: 0xA680) W-1 W-0 W-1 W-0 W-0 W-1 CCB<15:12> W-1 W-0 FREQB<11:8> bit 15 bit 8 W-1 W-0 W-0 W-0 W-0 W-0 W-0 W-0 FREQB<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 CCB<15:12>: Command Code bits The command code bits (1010b) are serially sent to the microcontro
MRF49XA REGISTER 2-7: W-1 RXCREG: RECEIVE CONTROL REGISTER (POR: 0x9080) W-0 W-0 W-1 W-0 CCB<15:11> W-0 W-0 FINTDIO W-0 DIORT<1:0> bit 15 bit 8 W-1 W-0 W-0 RXBW<2:0> W-0 W-0 RXLNA<1:0> W-0 W-0 W-0 DRSSIT<2:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 CCB<15:11>: Command Code bits The command code bits (10010b) are serially se
MRF49XA REGISTER 2-7: bit 2-0 RXCREG: RECEIVE CONTROL REGISTER (POR: 0x9080) (CONTINUED) DRSSIT<2:0>: Digital RSSI Threshold bits These bits can be set to indicate the incoming signal strength above a preset limit. The result enables or disables the DQDO bit (STSREG<7>). 111 = Reserved 110 = Reserved 101 = -73 dB 100 = -79 dB 011 = -85 dB 010 = -91 dB 001 = -97 dB 000 = -103 dB DS70590C-page 28 Preliminary © 2009-2011 Microchip Technology Inc.
MRF49XA REGISTER 2-8: W-1 BBFCREG: BASEBAND FILTER CONFIGURATION REGISTER (POR: 0xC22C) W-1 W-0 W-0 W-0 W-0 W-1 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-1 W-0 W-1 ACRLC MCRLC r FTYPE r W-1 W-0 W-0 DQTI<2:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000010b) are serially sent to
MRF49XA EQUATION 2-3: TABLE 2-7: DQIpar = 4 x (Deviation – TX/RXoffset)/Bit Rate DS70590C-page 30 DATA RATE VS. FILTER CAPACITOR VALUE Data Rate Preliminary Filter Capacitor Value 1.2 kbps 12 nF 2.4 kbps 8.2 nF 4.8 kbps 6.8 nF 9.6 kbps 3.3 nF 19.2 kbps 1.5 nF 38.4 kbps 680 pF 57.6 kbps 270 pF 115.2 kbps 150 pF 256 kbps 100 pF © 2009-2011 Microchip Technology Inc.
MRF49XA REGISTER 2-9: W-1 RXFIFOREG: RECEIVER FIFO READ REGISTER (POR: 0xB000) W-0 W-1 W-1 W-0 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 RXDB<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (10110000b) are serially sent to the microcontroller to identify the
MRF49XA REGISTER 2-10: W-1 FIFORSTREG: FIFO AND RESET MODE CONFIGURATION REGISTER (POR: 0xCA80) W-1 W-0 W-0 W-1 W-0 W-1 W-0 CCB<15:8> bit 15 bit 8 W-1 W-0 W-0 FFBC<3:0> W-0 W-0 W-0 W-0 W-0 SYCHLEN FFSC FSCF DRSTM bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001010b) are seriall
MRF49XA TABLE 2-8: SYNCHRONOUS CHARACTER SELECTION SYCHLEN SCL0 Synchronous Character 1 NA 0xD4 0xD4 (byte long) 0 0x2D 0xD4 0x2DD4 (word long) TABLE 2-9: RESET MODE SELECTION DRSTM Note: SCL1 Reset mode 1 Normal Reset 0 Sensitive Reset Condition Reset is triggered when VDD is below 250 mV Reset is triggered when VDD is below 1.6V and VDD glitch is greater than 600 mV See Appendix A: “Read Sequence and Packet Structures” for FIFO packet structures.
MRF49XA REGISTER 2-11: W-1 SYNBREG: SYNCHRONOUS BYTE CONFIGURATION REGISTER (POR: 0xCED4) W-1 W-0 W-0 W-1 W-1 W-1 W-0 CCB<15:8> bit 15 bit 8 W-1 W-1 W-0 W-1 W-0 W-1 W-0 W-0 SYNCB<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001110b) are serially sent to the microcontroller to i
MRF49XA REGISTER 2-12: W-1 DRSREG: DATA RATE VALUE SET REGISTER (POR: 0xC623) W-1 W-0 W-0 W-0 W-1 W-1 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-1 W-0 W-0 W-0 W-1 W-1 DRPV<6:0>(1) DRPE bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000110b) are serially sent to the microcontroller to ident
MRF49XA REGISTER 2-13: W-1 PMCREG: POWER MANAGEMENT CONFIGURATION REGISTER (POR: 0x8208) W-0 W-0 W-0 W-0 W-0 W-1 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 RXCEN BBCEN(1) W-0 TXCEN W-0 SYNEN W-1 OSCEN W-0 LBDEN W-0 W-0 (3) WUTEN CLKOEN bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (10000010
MRF49XA REGISTER 2-13: bit 0 Note 1: 2: 3: 4: PMCREG: POWER MANAGEMENT CONFIGURATION REGISTER (POR: 0x8208) (CONTINUED) CLKOEN: Clock Output Enable bit On-chip Reset or power-up clock output is enabled so that a processor can execute any special setup sequences as required by the designer(2). 1 = Disables the clock output 0 = Enables the clock output(4) This bit can be disabled to reduce current consumption. See BCSREG (Register 2-16) for programming details.
MRF49XA REGISTER 2-14: W-1 WTSREG: WAKE-UP TIMER VALUE SET REGISTER (POR: 0xE196) W-1 W-1 W-0 W-0 CCB<15:13> W-0 W-0 W-1 WTEV<4:0> bit 15 bit 8 W-1 W-0 W-0 W-1 W-0 W-1 W-1 W-0 WTMV<7:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 CCB<15:13>: Command Code bits The command code bits (111b) are serially sent to the microcontroller to
MRF49XA REGISTER 2-15: W-1 DCSREG: DUTY CYCLE VALUE SET REGISTER (POR: 0xC80E) W-1 W-0 W-0 W-1 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-0 W-0 W-1 W-1 W-1 DCMV<6:0> W-0 DCMEN bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001000b) are serially sent to the microcontroller to identi
MRF49XA REGISTER 2-16: W-1 BCSREG: BATTERY THRESHOLD DETECT AND CLOCK OUTPUT VALUE SET REGISTER (POR: 0xC000) W-1 W-0 W-0 W-0 W-0 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-0 W-0 COFSB<2:0> W-0 W-0 r W-0 W-0 W-0 LBDVB<3:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11000000b) are seria
MRF49XA REGISTER 2-17: W-1 PLLCREG: PLL CONFIGURATION REGISTER (POR: 0xCC77) W-1 W-0 W-0 W-1 W-1 W-0 W-0 CCB<15:8> bit 15 bit 8 W-0 W-1 — W-1 W-1 W-0 W-1 W-1 W-1 r PDDS PLLDD r PLLBWB CBTC<1:0> bit 7 bit 0 Legend: r = reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 CCB<15:8>: Command Code bits The command code bits (11001100b) are serially sent to the mic
Reg.
MRF49XA 3.0 FUNCTIONAL DESCRIPTION 3.1 Reset The MRF49XA is a low-power, Zero-IF, multi-channel FSK transceiver which operates in the 433, 868 and 915 MHz frequency bands. All the RF and baseband functions and processes are integrated in the MRF49XA. The device for its operation requires only a single, 10 MHz crystal as a reference source and an external, low-cost host microcontroller.
MRF49XA 3.1.2 POWER GLITCH RESET Spikes or glitches are found on the VDD line if the power supply filtering is not satisfactory, or the internal resistance of the power supply is very high. So, in this case, the Sensitive Reset mode needs to be enabled. Here, the device Reset occurs due to the transients present on the VDD line. The internal Reset block has two basic modes of operation: The Sensitive Reset mode is the default mode which can be changed using the DRSTM bit (FIFORSTREG<0>).
MRF49XA FIGURE 3-3: SENSITIVE RESET DISABLED V DD Reset Threshold Voltage (600 mV) Reset Ramp Line (100 mV/ms) 250 mV Time RESET Output (Pin 10) 3.1.3 H L SOFTWARE RESET The registers associated with Reset are: The Software Reset is initiated using the host microcontroller. The 0xFE00 command triggers this Reset only if the Sensitive Reset mode is enabled. The hardware automatically clears the bit(s) to their power-on state.
MRF49XA 3.2 VDD Line Filtering During the Reset event (caused by power-on, glitch on the supply line or Software Reset), the VDD line should be kept clean. Noise or a periodic disturbing signal superimposed on the supply voltage may prevent the device from getting out of the Reset state. To avoid this, adequate filters should be made available on the power supply lines to keep the distorting signal level below 100 mVp-p, in the DC-50 kHz range for 200 ms, from VDD ramp start.
MRF49XA 3.3 Power and Low Noise Amplifiers The PA is an open-collector, differential output with programmable output power which can directly drive a loop or dipole antenna, and with proper matching, can also drive a monopole antenna. An automatic antenna tuning circuit configured in the PA avoids the manual tuning during production and this offsets “hand effects”. TABLE 3-1: PROGRAMMABLE LOAD CAPACITANCE VALUE CAP3 CAP2 CAP1 CAP0 Load Capacitance 0 0 0 0 8.
MRF49XA 3.4.2 AUTO CRYSTAL OSCILLATOR When an interrupt occurs, irrespective of the OSCEN bit setting, the crystal oscillator automatically turns on to supply a clock signal to the microcontroller. After clearing all interrupts and reading the STSREG, the crystal oscillator is automatically turned off. The clock tail feature provides enough clock pulses for the microcontroller to enter the Low-Power mode.
MRF49XA 3.6 Crystal Selection Guidelines The crystal oscillator of MRF49XA requires a 10 MHz Parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF – 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF – 20 pF, so a variety of crystal types can be used.
MRF49XA 3.7 Automatic Frequency Control The AFC block operates in two modes and these modes depend on the strobe signals which are governed by the MFCS bit (AFCCREG<3>). The two operating modes are as follows: caused by the crystal tolerances. This method allows the use of a low-cost quartz crystal in the application and provides protection against interference. (AUTOMS1 = 1, AUTOMS0 = 0): The frequency offset is automatically calculated and the center frequency is corrected when the DIO is high.
© 2009-2011 Microchip Technology Inc.
MRF49XA 3.8 Initialization 3.9 Certain control register values must be initialized for the basic operations of MRF49XA. These values differ from the Power-on Reset values and provide improved operational parameters. These settings are normally made once after a Reset. After initialization, the MRF49XA device features can be configured for the application. Here, accessing a register is implied as a command to the MRF49XA device through the SPI port.
MRF49XA 3.9.1 SETTING INTERRUPTS 3.9.1.4 The device’s interrupt pin (IRO) signals one of eight interrupt events to the host microcontroller. The interrupt source in the microcontroller is read out from the transceiver through the SDO pin. The interrupt sources that are available are briefly described in the following subsections. 3.9.1.1 1. TXRXFIFO: Transmit Register or Receive FIFO bit Transmit mode: Transmit Register Ready bit This interrupt is generated when the Transmit register is empty.
MRF49XA 3.9.2.3 1. TXOWRXOF Transmit mode In this mode, the TXOWRXOF and TXRXFIFO bits are always set together. The IRO pin and its status bit remain active until the transmitter and the TX latch are switched off. 2. Receive mode In this mode, the TXOWRXOF and TXRXFIFO bits are always set together and can be cleared by reading the STSREG.
MRF49XA FIGURE 3-7: MRF49XA INTERRUPT GENERATION LOGIC TXRXFIFO TXCEN TXRXFIFO RXCEN RESET (Ext./Int.) TXOWRXOF TXCEN IRO TXOWRXOF RXCEN WUTINT WUTEN LCEXINT (INT) FINTDIO LBTD LBDEN © 2009-2011 Microchip Technology Inc.
MRF49XA 3.10 Baseband/Data Filtering A suitable bandwidth should be used to achieve various FSK deviation, data rate and crystal tolerance requirements. The filter structure is a 7th order, Butterworth low-pass with 40 dB suppression at twice the bandwidth frequency. Offset cancellation is done by using a high-pass filter, with a cutoff frequency below 7 kHz, in order to achieve the best possible frequency response in baseband and a good flat response in the pass band.
MRF49XA FIGURE 3-9: FSK MODULATED DEVIATION – MAXIMUM TX TO RX OFFSET 2 x deviation Amplitude 10 kHz + Data Rate Baseband Filter Characteristic Data Rate TX-RX Offset Frequency BBBW Programmable The baseband filtering type can also be selected between an analog filter and a digital filter. 3.10.1 ANALOG FILTERING MODE For analog filtering, a simple RC low-pass filter is used, along with a Schmitt Trigger circuit. The demodulator output is fed to the RCLKOUT/FCAP/FINT pin over a 10 kΩ resistor.
MRF49XA 3.11 Data Quality Indicator can prevent the crystal oscillator from starting, or the DQI signal will not go high, even when the quality of the received signal is good. The DQI is the digital processing part of the radio connected to the demodulator and functions when the receiver is on. This reports the reception of an FSK modulated RF signal. The DQI parameter setting defines how clean the incoming data stream would be stated as good data (valid FSK signal).
MRF49XA The DIO signal response time setting is configured through RXCREG and has the following modes of operation: • Default mode: The DIO is permanently connected to logic high. It always stays high independent of the receiving parameters. • Slow mode: The DIO signal goes high if the digital RSSI, DQI and Clock Recovery Lock (CR_LOCK) signals are present. It stays high until any of these signals are present and goes low when all three input signals are low.
MRF49XA TABLE 3-2: DIGITAL RSSI THRESHOLD LEVELS RSSI Threshold DRSSIT2 DRSSIT1 DRSSIT0 Reserved 1 1 1 Reserved 1 1 0 -73 1 0 1 -79 1 0 0 -85 0 1 1 -91 0 1 0 -97 0 0 1 -103 0 0 0 FIGURE 3-11: INPUT POWER VS. ANALOG RSSI VOLTAGE 1.2 1 0.6 RSSI (V) 0.8 0.4 0.2 0 -112 -102 -92 -82 -72 -62 -52 -42 Input Power (dBm) 3.13.1 RELATIONSHIP BETWEEN RSSI AND CLOCK RECOVERY 3.13.
MRF49XA 3.14 Power Management The Power Management Configuration enables/disables the following functions: • • • • • • • • register Receiver Transmitter Baseband Circuit Synthesizer Crystal Oscillator Low Battery Detect Circuit Wake-up Timer Clock Output Clock Output: The CLKOEN bit, when set, disables the oscillator clock output. On device Reset or power-up, the clock output is enabled so that a processor can begin execution of any special setup sequences as required by the designer.
MRF49XA From PMCREG, the following points are applicable when using the bit functionalities: • The chip enters Receive mode if both the TXCEN and RXCEN bits are set. • FSK/DATA/FSEL input is equipped with an internal pull-up resistor. To achieve minimum current consumption, do not pull this input to logic low in Sleep mode. • To enable the RF synthesizer, the crystal oscillator must be turned on. • To turn on the baseband circuits, the RF synthesizer and the crystal oscillator must be enabled.
© 2009-2011 Microchip Technology Inc. FIGURE 3-12: LOGIC CONNECTIONS BETWEEN POWER CONTROL BITS Enable Power Amplifier TXCEN Start TX Enable Power Amplifier Edge Detector LNA PA Enable RF Front End Clear TX Latch (If TX latch is used) Enable RF Synthesizer VCO and PLL Preliminary SYNEN Enable RF Synthesizer (Crystal Synthesizer must be ON) Start TX Clear TX Latch RXCEN TX Latch Enable RF Front End Enable Baseband Circuits Enable Crystal Oscillator Crystal Oscillator I/Q Demod.
MRF49XA 3.15 Low Duty Cycle Mode In Low Duty Cycle mode, the receiver periodically wakes up for a short period and checks for the valid FSK transmission in progress. The FSK transmission is detected in the frequency range determined by CFSREG and the baseband filter bandwidth is determined by the RXCREG. The on time is automatically extended until the DQI indicates a good received signal condition. completely and all other interrupts are cleared. The device then returns to the Low-Power Consumption mode.
MRF49XA 3.16 Sleep, Wake-up and Battery Operations The advanced interrupt handler circuit is configured in the transmitter to reduce the power consumption. As mentioned, the Sleep mode is the lowest power consumption mode in which the clock and all functional blocks of the device are disabled. In case of any interrupt, the device wakes up, switches to Active mode and an interrupt signal generated on the IRO pin indicates the change in state to the host microcontroller.
MRF49XA 3.17 TX Register Buffered Data Transmission In Data Transmission mode (enabled by the TXDEN bit (GENCREG<7>)), the TX data is clocked into one of the two 8-bit data registers. The transmitter starts to send the data from the first register (with the given bit rate) when the TXCEN bit (PMCREG<5>) is set. The initial value of the data registers (0xAA) can be used to generate preamble.
MRF49XA FIGURE 3-15: TX REGISTER BLOCK DIAGRAM (DURING TRANSMIT) TXCEN = 1 (During TX) SDI 8-Bit Shift Register SEL 10 Y Bit Rate SDO CLK 11 MUX SEL 1:8 Divider 10 SEL 8-Bit Shift Register 10 SCLK Y TX_DATA SDI Y CLK SDO 11 MUX 11 MUX Serial Bus Data © 2009-2011 Microchip Technology Inc. Note: The data registers’ content is initialized by clearing the TXCEN bit.
MRF49XA The device transmit sequence should be performed as follows: 1. 2. Enable the TX register by setting TXDEN = 1. The TX register is automatically filled with 0xAAAA, which can be used to generate preamble. 3. Enable the transmitter by setting TXCEN = 1. 4. The synthesizer and the PLL turns on, calibrates itself and the PA is automatically enabled. 5. The TX data transmission starts. 6. On completion of byte transmission, the IRO pin goes high and the SDO pin goes low simultaneously.
MRF49XA FIGURE 3-16: TX REGISTER USAGE Do not switch the TXCEN off here, because the TX Byte 1 is not transmitted out, it is only stored in the internal register Enabling the transmitter preloads the TX latch with 0xAAAA SPI Commands GENCREG (CS, SCK, SDI) TXDEN = 1 TX Latch TX Latch TX Byte 1 Dummy TX Byte PMCREG TXCEN = 1 PMCREG TXCEN = 0 GENCREG TXDEN = 0 TXCEN Enable Synthesizer/PA Synt.
MRF49XA 3.18 RX FIFO Buffered Data Read the device on the rising edge of the clock on the SCK pin. The serial interface is initialized every time if the CS signal is high. Figure 3-18 shows a simple receiver FIFO read over SPI lines. In the Receive Operating mode, the incoming data is clocked into a 16-bit FIFO buffer. The receive pin function configuration required for the FIFO operation is given in Table 3-4. The FIFOEN bit is in the GENCREG register and enables the receive FIFO.
MRF49XA 3.18.1 INTERRUPT MODE 3.18.2 The user can define the FIFO interrupt level (the number of received bits) which generates the FINT when the level is exceeded. In this case, the Status bits report the changed FIFO status. POLLING MODE When the FSEL signal is low, the FIFO output is connected directly to the SDO pin and its contents are clocked out by the SCK pin. Set the FIFO interrupt level to 1.
MRF49XA 3.19 RX-TX Frequency Alignment Method The RX-TX frequency offset occurs due to the differences in the actual reference frequency. To minimize this error, the same crystal type and the same PCB layout should be used for the crystal placement on the RX and TX PCBs. Also, see Section 3.6, Crystal Selection Guidelines. To verify the possible RX-TX offset, it is recommended to measure the CLK output of both transceivers with a high level of accuracy.
MRF49XA 4.0 APPLICATION DETAILS The application circuit of MRF49XA with a balun circuit is shown in Figure 4-1. FIGURE 4-1: APPLICATION CIRCUIT VDD C1 2 .2 u F IN T /D IO * RC7 SDI RC6 SCK RC5 CS RC4 RC3 IR O RC2 F S K /D A T A /F S E L * RC1 R C L K O U T /F C A P /F IN T * RC0 C LK O U T* OSC1 _____ M C LR 1 16 2 15 3 14 4 5 MRF49XA P IC ® M C U SDO C3 0 .0 1 u F C2 (see Table 2-2) C4* 2 .
MRF49XA 4.2 Antenna Design Considerations The MRF49XA is designed to drive a differential output, such as a dipole antenna or a loop antenna. The loop antenna is ideally suited for applications where compact size is required. The dipole is typically not a good option for compact designs due to its inherent size at resonance, and its space requirements around the ground plane, to be an efficient antenna. A monopole antenna can be used, along with a balun, or by using the matching circuit.
MRF49XA The following guidelines explain the requirements of the above mentioned layers. • It is important to keep the original PCB thickness, since any change will affect antenna performance (see total thickness of dielectric) or microstrip lines’ characteristic impedance. • For good transmit and receive performance, the trace lengths at RF pins must be kept as short as possible. Using small, surface mount components (in 0402/0603 package) yields good performance and keeps the RF circuit small.
MRF49XA 4.5 MRF49XA Schematic and Bill of Materials 4.5.1 SCHEMATIC FIGURE 4-5: MRF49XA SCHEMATIC +3.3V C1 RSSIO C2 0.01 uF C3 2.2 uF 6.3V C4 1000 pF +3.3V INT/DIO L1 U1 MRF49XA SDI SCK __ CS SDO __ IRO __ FSEL FINT TP1 CLK TP2 GND 1 2 3 4 5 6 7 89 C5 C6 J1 50Ω ANT __ 16 SDI INT/DIO 15 SCK RSSIO __ 14 VDD CS 13 SDO RFN __ 12 IRO RFP ___ 11 FSK/DATA/FSEL VSS ____ 10 RCLK OUT/FCAP/FINT RESET CLKOUT RFXTL/EXTREF L2 L3 C7 X1 10 MHz ___ RESET Freq.
MRF49XA 4.5.2 BILL OF MATERIALS TABLE 4-2: MRF49XA: 433 MHz BILL OF MATERIALS Designator Value C1 200 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H201JA01D C5 2.7 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H2R7CZ01D C6 68 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H680JA01D C7 5.
MRF49XA TABLE 4-3: MRF49XA: 868/915 MHz BILL OF MATERIALS Designator Value C1 33 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H330JA01D C5 1.2 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H1R2CZ01D C6 27 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H270JA01D C7 2.7 pF Capacitor, Ceramic, 50V, C0G, SMT 0603 Murata GRM1885C1H2R7CZ01D L1 100 nH Inductor, Multilayer, 5%, SMT 0603 L2 8.
MRF49XA 5.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Temperature under bias ........................................................................................................................... -40°C to +85°C Storage temperature .............................................................................................................................. -55°C to +125°C Lead temperature (soldering, max 10s) ................................................................................
MRF49XA TABLE 5-1: RECOMMENDED OPERATING CONDITIONS Parameters Min Typ Max Unit Operating Temperature -40 — +85 °C Supply Voltage for RF, Analog and Digital Circuits 2.2 — 3.8 V Supply Voltage for Digital I/O 2.2 3.3 3.8 V DC Voltage on Open-Collector Outputs (RFP, RFN)(1,2) VDD–1.5 — VDD+1.5 V AC Peak Voltage on Open-Collector Outputs (RFP, RFN)(1) VDD–1.5 — VDD+1.5 V Note 1: 2: At minimum, VDD – 1.5V cannot be lower than 1.2V. At maximum, VDD + 1.5V cannot be higher than 5.
MRF49XA TABLE 5-4: RECEIVER AC CHARACTERISTICS(1) Parameters Receiver Sensitivity Condition Min Typ Max Unit (2) — -112 — dBm (2) — -110 — dBm (2) 915 MHz band — -109 — dBm LNA: High Gain 0 — — dBm 433 MHz band 868 MHz band Maximum RF Input Power RF Input Capacitance — — 1 — pF Receiver Spurious Emission — — — -60 dBm mode 0 — 67 — kHz Mode 1 — 134 — kHz Mode 2 — 200 — kHz Mode 3 — 270 — kHz Mode 4 — 340 — kHz Receiver BW Mode 5 RSSI Range
MRF49XA TABLE 5-5: TRANSMITTER AC CHARACTERISTICS(1) Parameters RF Carrier Frequency Maximum RF Output Power Condition Min Typ Max Unit 433 MHz band, 2.5 kHz resolution 430.24 — 439.75 MHz 868 MHz band, 5.0 kHz resolution 860.48 — 879.51 MHz 915 MHz band, 7.5 kHz resolution 900.72 — 929.27 MHz 433 MHz @ 50Ω load — 7 — dBm 868 MHz @ 50Ω load — 5 — dBm 915 MHz @ 50Ω load — 5 — dBm RF Output Power Control Range In steps of 8 Pmax – 17.
MRF49XA TABLE 5-7: OTHER TIMING PARAMETERS AC CHARACTERISTICS(1) Parameters Condition Min Typ Max Unit Transmitter Switch On Time Synthesizer off, crystal oscillator on with 10 MHz step — 250 — μs Receiver Switch On Time Synthesizer off, crystal oscillator on with 10 MHz step — 250 — μs Transmitter to Receiver Switch Time Synthesizer and crystal oscillator on during TX/RX change with 10 MHz step — 150 — μs Receiver to Transmitter Switch Time Synthesizer and crystal oscillator on d
MRF49XA 5.
MRF49XA 5.2 Typical Performance Characteristics CHANNEL SELECTIVITY AND BLOCKING(1,2) FIGURE 5-2: 80 70 Suppression (dB) 60 50 40 30 20 434 MHz 10 868 MHz ETSI 0 0 1 2 3 4 5 6 7 8 9 10 11 12 CW Interferer Offset with respect to Carrier (MHz) Note 1: 2: LNA gain maximum, filter bandwidth 67 kHz, data rate 9.6 kbps, AFC switched off, FSK deviation ±45 kHz, VDD = 2.7V. The ETSI limit given in the figure is drawn by taking -106 dBm at 9.
MRF49XA FIGURE 5-3: BER CURVES IN 433 MHz BAND BER Curves in 433 MHz Band 1.0E+00 1.0E-01 BER 1.0E-02 1.0E-03 1.0E-04 1.2k 9.6k 19.2k 115.2k 1.0E-05 1.0E-06 -120 -115 -110 -105 -100 -95 -90 Input Power (dBm) FIGURE 5-4: BER CURVES IN 868 MHz BAND BER Curves in 868 MHz Band 1.0E+00 1.0E-01 BER 1.0E-02 1.0E-03 1.0E-04 1.2k 9.6k 19.2k 115.2k 1.0E-05 1.0E-06 -115 -110 -105 -100 -95 -90 -85 Input Power (dBm) DS70590C-page 86 Preliminary © 2009-2011 Microchip Technology Inc.
MRF49XA Table 5-9 shows the optimal receiver BBBW and transmitter deviation frequency (ΔfFSK) settings for different data rates, considering no TX/RX offset frequency. If the TX/RX offset (for example, due to crystal tolerances) has to be taken into account, increase the BW accordingly. TABLE 5-9: Baud Rate RX BW AND TX DEVIATION FREQUENCY FOR DIFFERENT BAUD RATES 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 57.6 kbps 115.
MRF49XA FIGURE 5-5: RECEIVER SENSITIVITY OVER AMBIENT TEMPERATURE (433 MHz, 2.4 kbps, ΔfFSK: 45 kHz, BW: 67 kHz) Receiver Sensitivity over Ambient Temperature for 433 MHz -100 Power Level (dBm) -103 2.2V -106 2.7V 3.3V -109 3.8V -112 -115 -50 -25 0 25 50 75 100 Temperature (°C) FIGURE 5-6: RECEIVER SENSITIVITY OVER AMBIENT TEMPERATURE (868 MHz, 2.4 kbps, ΔfFSK: 45 kHz, BW: 67 kHz) Receiver Sensitivity over Ambient Temperature for 868 MHz -100 Power Level (dBm) -103 2.2V -106 2.7V 3.
MRF49XA 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 16-Lead TSSOP Example XXXXXXXX YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: 49XA/ST e3 0910 017 Product-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
MRF49XA 6.2 Package Details This section provides the technical details of the packages. 16-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70590C-page 90 Preliminary © 2009-2011 Microchip Technology Inc.
MRF49XA 16-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
MRF49XA 16-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70590C-page 92 Preliminary © 2009-2011 Microchip Technology Inc.
MRF49XA APPENDIX A: READ SEQUENCE AND PACKET STRUCTURES Figure 1 shows the STSREG read sequence with FIFO read as an example.
MRF49XA NOTES: DS70590C-page 94 Preliminary © 2009-2011 Microchip Technology Inc.
MRF49XA APPENDIX B: REVISION HISTORY Revision A (March 2009) This is the initial released version of this document. Revision B (June 2009) Major updates are done throughout the document. Revision C (November 2011) Minor corrections such as figures, language and formatting updates are incorporated throughout the document. © 2009-2011 Microchip Technology Inc.
MRF49XA NOTES: DS70590C-page 96 Preliminary © 2009-2011 Microchip Technology Inc.
MRF49XA INDEX F A Absolute Maximum Ratings ................................................ 79 AC Characteristics Other Timing Parameters............................................ 83 PLL Parameters .......................................................... 82 Receiver...................................................................... 81 Transmitter.................................................................. 82 Antenna Design Considerations .........................................
MRF49XA RESET ........................................................................ 12 RFN............................................................................. 12 RFP ............................................................................. 12 RFXTL/EXTREF ......................................................... 12 RSSIO......................................................................... 12 SCK............................................................................. 11 SDI .........
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MRF49XA PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Example: a) b) Device MRF49XA: Sub-GHz RF Transceiver Temperature Range I Package ST = TSSOP (Lead Plastic Thin Shrink Small Outline, No Lead) T = Tape and Reel MRF49XA-I/ST: Industrial temperature, TSSOP package. MRF49XAT-I/ST: Industrial temperature, TSSOP package, tape and reel.
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