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MCP9843/98243

4.0 SERIAL COMMUNICATION

4.1 2-Wire Standard Mode I

C™

Protocol-Compatible Interface

The MCP9843/98243 serial clock input (SCL) and the

bidirectional serial data line (SDA) form a 2-wire

bidirectional Standard mode I

C compatible

communication port (refer to the Input/Output Pin DC

Characteristics (Note 1) Table and Sensor And

EEPROM Serial Interface Timing Specifications

Table).

The following bus protocol has been defined:

TABLE 4-1: MCP9843/98243 SERIAL BUS

PROTOCOL DESCRIPTIONS

4.1.1 DATA TRANSFER

Data transfers are initiated by a Start condition

(START), followed by a 7-bit device address and a

read/write bit. An Acknowledge (ACK) from the slave

confirms the reception of each byte. Each access must

be terminated by a Stop condition (STOP).

Repeated communication is initiated after t

B-FREE

This device does not support sequential register read/

write. Each register needs to be addressed using the

This device supports the Receive Protocol. The

read. Each repeated read or receive begins with a Start

condition and address byte. The MCP9843/98243

retain the previously selected register. Therefore, they

output data from the previously-specified register

(repeated pointer specification is not necessary).

4.1.2 MASTER/SLAVE

The bus is controlled by a master device (typically a

microcontroller) that controls the bus access and

generates the Start and Stop conditions. The

MCP9843/98243 is a slave device and does not control

other devices in the bus. Both master and slave

devices can operate as either transmitter or receiver.

However, the master device determines which mode is

activated.

4.1.3 START/STOP CONDITION

A high-to-low transition of the SDA line (while SCL is

high) is the Start condition. All data transfers must be

preceded by a Start condition from the master. A low-

to-high transition of the SDA line (while SCL is high)

signifies a Stop condition.

If a Start or Stop condition is introduced during data

transmission, the MCP9843/98243 releases the bus.

All data transfers are ended by a Stop condition from

the master.

4.1.4 ADDRESS BYTE

Following the Start condition, the host must transmit an

8-bit address byte to the MCP9843/98243. The

address for the MCP9843/98243 Temperature Sensor

is ‘0011,A2,A1,A0’ in binary, where the A2, A1 and

A0 bits are set externally by connecting the

corresponding pins to V

‘1’ or GND ‘0’. The 7-bit

address transmitted in the serial bit stream must match

the selected address for the MCP9843/98243 to

respond with an ACK. Bit 8 in the address byte is a

read/write bit. Setting this bit to ‘1’ commands a read

operation, while ‘0’ commands a write operation (see

Figure 4-1).

FIGURE 4-1: Device Addressing.

Term Description

Master The device that controls the serial bus,

typically a microcontroller.

Slave The device addressed by the master,

such as the MCP9843/98243.

Transmitter Device sending data to the bus.

Receiver Device receiving data from the bus.

START A unique signal from master to initiate

serial interface with a slave.

STOP A unique signal from the master to

terminate serial interface from a slave.

Read/Write A read or write to the MCP9843/98243

registers.

ACK A receiver Acknowledges (ACK) the

reception of each byte by polling the

bus.

NAK A receiver Not-Acknowledges (NAK) or

releases the bus to show End-of-Data

(EOD).

Busy Communication is not possible

because the bus is in use.

Not Busy The bus is in the idle state, both SDA

and SCL remain high.

Data Valid SDA must remain stable before SCL

becomes high in order for a data bit to

be considered valid. During normal

data transfers, SDA only changes state

while SCL is low.

123456789

SCL

SDA

0 0 1 1 A2 A1 A0

Start

Address Byte

Slave

Address

R/W

MCP9843/98243 Response

Code

Address