Datasheet

2010-2013 Microchip Technology Inc. DS20002266E-page 37
MCP79410/MCP79411/MCP79412
10.0 ON-BOARD MEMORY
The MCP7941X has both on-board EEPROM memory
and battery-backed SRAM. The SRAM is arranged as
64 bytes and is retained when the V
CC supply is
removed, provided the V
BAT supply is present and
enabled. The EEPROM is organized as 128 x 8 bytes.
The EEPROM is nonvolatile memory and does not
require the V
BAT supply for retention.
10.1 SRAM/RTCC
FIGURE 10-1: SRAM/RTCC BYTE WRITE
FIGURE 10-2: SRAM/RTCC MULTIPLE BYTE WRITE
The 64 bytes of user SRAM are at location 0x20h and
can be accessed during the time when the RTCC is
being internally updated. Upon POR, the SRAM will be
in an undefined state.
Writing to the SRAM and RTCC is accomplished in a
similar way to writing to the EEPROM (as described
later in this document) with the following consider-
ations:
There is no page. The entire 64 bytes of SRAM or
32 bytes of RTCC register can be written in one
command.
The SRAM allows an unlimited number of read/
write cycles.
The RTCC and SRAM are not accessible when
the device is running on the external V
BAT supply.
The RTCC and SRAM are separate blocks. The
SRAM array may be accessed during an RTCC
update.
Read and write access is limited to either the
RTCC register block or the SRAM array. The
Address Pointer will rollover to the start of the
addressed block.
Data written to the RTCC and SRAM are on a per
byte basis.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
DATA
S
T
O
P
A
C
K
A
C
K
A
C
K
S
1101 01
11
P0
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
DATA BYTE 0
S
T
O
P
A
C
K
A
C
K
A
C
K
DATA BYTE N
A
C
K
S
1101 0
111
P
0
Note: Entering an address past 0x5F for an
SRAM operation will result in the
MCP7941X not acknowledging the
address.