Datasheet

 2010-2013 Microchip Technology Inc. DS20002266E-page 35
MCP79410/MCP79411/MCP79412
FIGURE 9-2: ACKNOWLEDGE TIMING
9.1.2 DEVICE ADDRESSING AND OPERATION
A control byte is the first byte received following the
Start condition from the master device (Figure 9-2).
The control byte consists of a control code; for the
MCP7941X this is set as ‘1010111X’ for read (0xAF)
and write (0xAE) operations for the EEPROM.
The control byte for accessing the SRAM and RTCC
registers are set to ‘1101111X’ (0xDF for a read, 0xDE
for a write). The RTCC registers and the SRAM share
the same address space.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected. The next byte received defines the address of
the data byte (Figure 9-3). The upper address bits are
transferred first, followed by the Least Significant bits
(LSb).
Following the Start condition, the MCP7941X monitors
the SDA bus, checking the device type identifier being
transmitted. Upon receiving an ‘1010111X’ or
‘1101111X’ code, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W
bit, the MCP7941X will select a read
or write operation.
FIGURE 9-3: CONTROL BYTE AND ADDRESS SEQUENCE BIT ASSIGNMENTS
SCL
987654321123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
1 010 R/W
A7
A
0
••••••
EEPROM CONTROL BYTE
ADDRESS BYTE
CONTROL
CODE
111
1 101 R/W
A7
A
0
••••••
SRAM/RTCC CONTROL BYTE
ADDRESS BYTE
CONTROL
CODE
111