Datasheet

2012 Microchip Technology Inc. Preliminary DS22292A-page 15
MCP7940M
5.0 ON BOARD MEMORY
The MCP7940M has 64 x 8 bytes of on-chip SRAM.
5.1 SRAM
FIGURE 5-1: SRAM/RTCC BYTE WRITE
FIGURE 5-2: SRAM/RTCC MULTIPLE BYTE WRITE
The 64 bytes of user SRAM are at location 0x20h and
can be accessed during an RTCC update. Upon POR
the SRAM will be in an undefined state.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
DATA
S
T
O
P
A
C
K
A
C
K
A
C
K
S 1101 01
11
P
x
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
DATA BYTE 0
S
T
O
P
A
C
K
A
C
K
A
C
K
DATA BYTE N
A
C
K
S 1101 0
111
P
x
Note: Entering an address past 5F for an SRAM
operation will result in the MCP7940M not
acknowledging the address.