Datasheet

MCP73811/2
DS22036B-page 14 © 2007 Microchip Technology Inc.
6.1.1.2 Thermal Considerations
The worst-case power dissipation in the battery
charger occurs when the input voltage is at the
maximum and the device has transitioned from the
Preconditioning mode to the Constant-current mode. In
this case, the power dissipation is:
EQUATION 6-1:
Power dissipation with a 5V, ±10% input voltage source
is:
EQUATION 6-2:
This power dissipation with the battery charger in the
SOT-23-5 package will cause thermal regulation to be
entered as depicted in Figure 6-3.
6.1.1.3 External Capacitors
The MCP73811/2 is stable with or without a battery
load. In order to maintain good AC stability in the
Constant-voltage mode, a minimum capacitance of
1 µF is recommended to bypass the V
BAT
pin to V
SS
.
This capacitance provides compensation when there is
no battery load. In addition, the battery and intercon-
nections appear inductive at high frequencies. These
elements are in the control feedback loop during
Constant-voltage mode. Therefore, the bypass
capacitance may be necessary to compensate for the
inductive nature of the battery pack.
Virtually any good quality output filter capacitor can be
used, independent of the capacitor’s minimum
Effective Series Resistance (ESR) value. The actual
value of the capacitor (and its associated ESR)
depends on the output load current. A 1 µF ceramic,
tantalum or aluminum electrolytic capacitor at the
output is usually sufficient to ensure stability for output
currents up to a 500 mA.
6.1.1.4 Reverse-Blocking Protection
The MCP73811/2 provides protection from a faulted or
shorted input. Without the protection, a faulted or
shorted input would discharge the battery pack through
the body diode of the internal pass transistor.
6.1.1.5 Charge Inhibit
The charge enable input pin (CE) can be used to
terminate a charge at any time during the charge cycle,
as well as to initiate a charge cycle or initiate a recharge
cycle.
Driving the input to a logic High enables the device.
Driving the input to a logic Low disables the device and
terminates a charge cycle. When disabled, the device’s
supply current is reduced to 50 µA, typically.
6.2 PCB Layout Issues
For optimum voltage regulation, place the battery pack
as close as possible to the device’s V
BAT
and V
SS
pins,
recommended to minimize voltage drops along the
high current-carrying PCB traces.
If the PCB layout is used as a heatsink, adding many
vias in the heatsink pad can help conduct more heat to
the backplane of the PCB, thus reducing the maximum
junction temperature. Figures 6-3 and 6-4 depict a
typical layout with PCB heatsinking.
FIGURE 6-3: Typical Layout (Top).
FIGURE 6-4: Typical Layout (Bottom).
PowerDissipation V
DDMAX
V
PTHMIN
–()I
REGMAX
×=
Where:
V
DDMAX
= the maximum input voltage
I
REGMAX
= the maximum fast charge current
V
PTHMIN
= the minimum transition threshold
voltage
PowerDissipation 5.5V 2.7V–()500mA × 1.4W==
C
OUT
R
PROG
C
IN
MCP73812
V
BAT
V
DD
V
SS
V
BAT
V
SS
V
DD