Datasheet
© 2012 Microchip Technology Inc. DS25127A-page 21
MCP6V31/1U
4.2.1.3 Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1, Absolute Maximum
Ratings †). This requirement is independent of the volt-
age limits discussed previously.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R
1
and R
2
limit the possible
current in or out of the input pins (and into D
1
and D
2
).
The diode currents will dump onto V
DD
.
FIGURE 4-6: Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of
resistors R
1
and R
2
. In this case, the currents through
the diodes D
1
and D
2
need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
IN
+ and
V
IN
–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
CM
) is below ground (V
SS
); see
Figure 2-17.
4.2.2 RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V31/1U zero-drift
op amps is V
DD
–20mV (minimum) and V
SS
+20mV
(maximum) when R
L
=10kΩ is connected to V
DD
/2
and V
DD
= 5.5V. Refer to Figure 2-19 and Figure 2-20
for more information.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.3 Application Tips
4.3.1 INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC
1
and TC
2
) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
EQUATION 4-1:
4.3.2 DC GAIN PLOTS
Figures 2-9 to 2-11 are histograms of the reciprocals
(in units of µV/V) of CMRR, PSRR and A
OL
,
respectively. They represent the change in input offset
voltage (V
OS
) with a change in common mode input
voltage (V
CM
), power supply voltage (V
DD
) and output
voltage (V
OUT
).
The 1/A
OL
histogram is centered near 0 µV/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise and tester limitations, not unstable behavior.
Production tests make multiple V
OS
measurements,
which validates an op amp's stability; an unstable part
would show greater V
OS
variability, or the output would
stick at one of the supply rails.
4.3.3 OFFSET AT POWER UP
When these parts power up, the input offset (V
OS
)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like t
ODR
), in addition to the startup time (like
t
STR
).
It can be simple to avoid this extra startup time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (R
F
) is another method.
V
1
R
1
V
DD
D
1
min(R
1
,R
2
)>
V
SS
–min(V
1
,V
2
)
2mA
V
OUT
V
2
R
2
D
2
min(R
1
,R
2
)>
max(V
1
,V
2
)–V
DD
2mA
U
1
MCP6V3X
V
OS
T
A
() V
OS
TC
1
Δ
TTC
2
Δ
T
2
++=
Where:
∆T=T
A
–25°C
V
OS
(T
A
) = input offset voltage at T
A
V
OS
= input offset voltage at +25°C
TC
1
= linear temperature coefficient
TC
2
= quadratic temperature coefficient