Datasheet

© 2011 Microchip Technology Inc. DS25007B-page 25
MCP6V26/7/8
4.3.6 CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These auto-zeroed op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
series resistor at the output (R
ISO
in Figure 4-7)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
FIGURE 4-7: Output Resistor, R
ISO
,
Stabilizes Capacitive Loads.
Figure 4-8 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
2
). The y-axis is
the normalized resistance (G
N
R
ISO
).
G
N
is the circuit’s noise gain. For non-inverting gains,
G
N
and the Signal Gain are equal. For inverting gains,
G
N
is 1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
FIGURE 4-8: Recommended R
ISO
values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6V26/7/8 SPICE macro
model are helpful.
4.3.7 STABILIZING OUTPUT LOADS
This family of auto-zeroed op amps has an output
impedance (Figure 2-31 and Figure 2-32) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low
resistance near the part’s bandwidth. This large phase
shift can cause stability problems.
Figure 4-9 shows that the load on the output is
(R
L
+R
ISO
)||(R
F
+R
G
), where R
ISO
is before the load
(like Figure 4-7). This load needs to be large enough to
maintain stability; it should be at least (2 kΩ)/G
N
.
FIGURE 4-9: Output Load.
4.3.8 GAIN PEAKING
Figure 4-10 shows an op amp circuit that represents
non-inverting amplifiers (V
M
is a DC voltage and V
P
is
the input) or inverting amplifiers (V
P
is a DC voltage
and V
M
is the input). The capacitances C
N
and C
G
rep-
resent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(C
CM
), board parasitic capacitance and any capacitor
placed in parallel. The capacitance C
FP
represents the
parasitic capacitance coupling the output and
non-inverting input pins.
FIGURE 4-10: Amplifier with Parasitic
Capacitance.
C
G
acts in parallel with R
G
(except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
C
G
also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing C
G
or R
F
||R
G
.
C
N
and R
N
form a low-pass filter that affects the signal
at V
P
. This filter has a single real pole at 1/(2πR
N
C
N
).
R
ISO
C
L
V
OUT
U
1
MCP6V2X
1
10
100
1000
1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
C
L
/G
N
2
(F)
Recommended G
N
R
ISO
()
100p 1n 10n 100n 1μ
1
10
100
1k
G
N
= 1
G
N
= 2
G
N
= 5
G
N
 10
R
G
R
F
V
OUT
R
L
C
L
U
1
MCP6V2X
R
F
C
G
R
N
V
OUT
U
1
MCP6V2X
R
G
V
M
V
P
C
FP
C
N