Datasheet

© 2011 Microchip Technology Inc. DS25007B-page 23
MCP6V26/7/8
4.2 Other Functional Blocks
4.2.1 RAIL-TO-RAIL INPUTS
The input stage of the MCP6V26/7/8 op amps use two
differential CMOS input stages in parallel. One
operates at low common mode input voltage (V
CM
,
which is approximately equal to V
IN
+ and V
IN
– in
normal operation) and the other at high V
CM
. With this
topology, the input operates with V
CM
up to V
DD
+0.2V,
and down to V
SS
– 0.15V, at +25°C (see Figure 2-18).
The input offset voltage (V
OS
) is measured at
V
CM
=V
SS
– 0.15V and V
DD
+ 0.2V to ensure proper
operation.
The transition between the input stages occurs when
V
CM
≈ V
DD
–1.2V (see Figure 2-7 and Figure 2-8). For
the best distortion and gain linearity, with non-inverting
gains, avoid this region of operation.
4.2.1.1 Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-43 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.1.2 Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings †). This requirement is independent of the
current limits discussed later on.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
over-voltage conditions, and to minimize input bias
current (I
B
).
FIGURE 4-4: Simplified Analog Input ESD
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below V
SS
. They also
clamp any voltages that are well above V
DD
; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond V
DD
) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach to protecting these
inputs. D
1
and D
2
may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode-
connected FETs for low leakage.
FIGURE 4-5: Protecting the Analog Inputs
Against High Voltages.
4.2.1.3 Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1, Absolute
Maximum Ratings †). This requirement is
independent of the voltage limits previously discussed.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R
1
and R
2
limit the possible
current in or out of the input pins (and into D
1
and D
2
).
The diode currents will dump onto V
DD
.
FIGURE 4-6: Protecting the Analog Inputs
Against High Currents.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
V
DD
D
1
V
OUT
V
2
D
2
U
1
MCP6V2X
V
1
R
1
V
DD
D
1
min(R
1
,R
2
)>
V
SS
–min(V
1
,V
2
)
2mA
V
OUT
V
2
R
2
D
2
min(R
1
,R
2
)>
max(V
1
,V
2
)–V
DD
2mA
U
1
MCP6V2X