Datasheet

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MCP6V26/7/8

Features

• High DC Precision:

-V

Drift: ±50 nV/°C (maximum)

-V

: ±2 µV (maximum)

-A

: 125 dB (minimum)

- PSRR: 125 dB (minimum)

- CMRR: 120 dB (minimum)

-E

: 1.0 µV

P-P

(typical), f = 0.1 Hz to 10 Hz

-E

: 0.32 µV

P-P

(typical), f = 0.01 Hz to 1 Hz

• Low Power and Supply Voltages:

-I

: 620 µA/amplifier (typical)

- Wide Supply Voltage Range: 2.3V to 5.5V

•Easy to Use:

- Rail-to-Rail Input/Output

- Gain Bandwidth Product: 2 MHz (typical)

- Unity Gain Stable

- Available in Single and Dual

- Single with Chip Select (CS

): MCP6V28

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• Portable Instrumentation

• Sensor Conditioning

• Temperature Measurement

• DC Offset Correction

• Medical Instrumentation

Design Aids

• SPICE Macro Models

•FilterLab

Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Related Parts

Parts with lower power, lower bandwidth and higher

noise:

• MCP6V01/2/3: Spread clock

• MCP6V06/7/8: Non-spread clock

Description

The Microchip Technology Inc. MCP6V26/7/8 family of

operational amplifiers provides input offset voltage

correction for very low offset and offset drift. These

devices have a wide gain bandwidth product (2 MHz,

typical) and strongly reject switching noise. They are

unity gain stable, have no 1/f noise, and have good

power supply rejection ratio (PSRR) and common

mode rejection ratio (CMRR). These products operate

with a single supply voltage as low as 2.3V, while

drawing 620 µA/amplifier (typical) of quiescent current.

The Microchip Technology Inc. MCP6V26/7/8 op amps

are offered as a single (MCP6V26), single with Chip

Select (CS

) (MCP6V28) and dual (MCP6V27). They

were designed using an advanced CMOS process.

Package Types (top view)

–

OUT

NCNC

INA

–

OUTA

OUTB

INB

–

INB

MCP6V26

MSOP, SOIC

MCP6V27

MSOP, SOIC

–

OUT

MCP6V28

MSOP, SOIC

INA

–

OUTA

OUTB

INB

–

INB

MCP6V27

4×4 DFN *

* Includes Exposed Thermal Pad (EP); see Ta ble 3- 1.

–

OUT

MCP6V26

2×3 TDFN *

–

OUT

MCP6V28

2×3 TDFN *

620 µA, 2 MHz Auto-Zeroed Op Amps

Summary of content (50 pages)

PAGE 1
MCP6V26/7/8 620 µA, 2 MHz Auto-Zeroed Op Amps Features Description • High DC Precision: - VOS Drift: ±50 nV/°C (maximum) - VOS: ±2 µV (maximum) - AOL: 125 dB (minimum) - PSRR: 125 dB (minimum) - CMRR: 120 dB (minimum) - Eni: 1.0 µVP-P (typical), f = 0.1 Hz to 10 Hz - Eni: 0.32 µVP-P (typical), f = 0.01 Hz to 1 Hz • Low Power and Supply Voltages: - IQ: 620 µA/amplifier (typical) - Wide Supply Voltage Range: 2.3V to 5.
PAGE 2
MCP6V26/7/8 Typical Application Circuit 10 kΩ 10 kΩ VIN VOUT 10 kΩ 10 nF 500 kΩ 5 kΩ 10 kΩ VDD/2 U1 MCP6V26 U2 MCP661 VDD/2 Offset Voltage Correction for Power Driver DS25007B-page 2 © 2011 Microchip Technology Inc.
PAGE 3
MCP6V26/7/8 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. †† See Section 4.2.1, Rail-to-Rail Inputs.
PAGE 4
MCP6V26/7/8 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6). Parameters Sym Min Typ Max Units Conditions Common-Mode Input Voltage Range Low VCML — — VSS − 0.15 V (Note 2) Common-Mode Input Voltage Range High VCMH VDD + 0.
PAGE 5
MCP6V26/7/8 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND (refer to Figure 1-5 and Figure 1-6). Parameters Sym Min Typ Max Units Conditions Amplifier AC Response Gain Bandwidth Product GBWP — 2.0 — MHz Slew Rate SR — 1.0 — V/µs Phase Margin PM — 65 — ° Eni — 0.32 — µVP-P f = 0.01 Hz to 1 Hz Eni — 1.
PAGE 6
MCP6V26/7/8 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kW to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6). Parameters Sym Min Typ Max Units RPD 3 5 — MΩ CS Logic Threshold, Low VIL VSS — 0.
PAGE 7
MCP6V26/7/8 1.3 Timing Diagrams 1.4 2.3V to 5.5V 2.3V VDD 0V tSTR VOS + 50 µV VOS Test Circuits The circuits used for the DC and AC tests are shown in Figure 1-5 and Figure 1-6. Lay the bypass capacitors out as discussed in Section 4.3.10, Supply Bypassing and Filtering. RN is equal to the parallel combination of RF and RG to minimize bias current effects. VOS – 50 µV VDD RN VIN FIGURE 1-1: Amplifier Start Up.
PAGE 8
MCP6V26/7/8 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 9
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. 30% FIGURE 2-10: 0.4 0.3 0.2 0.1 0.0 0.4 0.3 0.2 0.1 0.0 155 25% VDD = 5.5V 15% DC Open-Loop Gain. 160 CMRR, PSRR (dB) Percentage of Occurrences FIGURE 2-11: 20 Samples TA = +25°C 20% -0.1 1/AOL (µV/V) FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. 30% VDD = 5.5V VDD = 2.3V -0.
PAGE 10
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. 10n 10,000 Input Bias, Offset Currents (A) DC Open-Loop Gain (dB) 160 155 150 1n 1,000 VDD = 5.5V VDD = 2.3V 145 140 135 130 125 120 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 1p 1 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) Input Current Magnitude (A) 1.E-04 100µ 1.E-05 10µ 100 IB 50 1.E-06 1µ 1.
PAGE 11
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. Other DC Voltages and Currents -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature. © 2011 Microchip Technology Inc. 6.0 5.5 5.0 6.5 6.5 6.0 5.5 5.0 4.5 4.0 15% 10% 5% 0% 1.35 -50 20% 1.34 0 25% 1.33 VDD = 2.3V 30% 820 Samples 1 Wafer Lot TA = +25°C 1.
PAGE 12
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. 1.8 POR Trip Voltage (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature. DS25007B-page 12 © 2011 Microchip Technology Inc.
PAGE 13
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. PSRR+ PSRR- CMRR and PSRR vs. -240 -270 10M 1.E+07 Open-Loop Gain (dB) 0 -30 50 -60 40 -90 ∠AOL 30 20 10 0 -120 -150 -180 | AOL | -210 -10 -20 1k 1.E+03 -240 10k 100k 1M 1.E+04 1.E+05 1.E+06 Frequency (Hz) -270 10M 1.E+07 FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 5.5V. © 2011 Microchip Technology Inc. 3.
PAGE 14
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. VDD = 2.3V Closed-Loop Output Impedance (Ω) 1.E+04 10k 1.E+03 1k 1.E+02 100 10 1.E+01 1.E+001 100k 1.0E+05 G = 1 V/V G = 11 V/V G = 101 V/V 1M 10M 1.0E+06 1.0E+07 Frequency (Hz) 100M 1.0E+08 FIGURE 2-31: Closed-Loop Output Impedance vs. Frequency with VDD = 2.3V. 10 VDD = 2.3V Maximum Output Voltage Swing (VP-P) 1.
PAGE 15
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. Input Noise and Distortion VDD = 5.5V VDD = 2.3V 1,000 100 100 1,000 100 eni 10 Eni(0 Hz to f) 10 1 100 100k 110E 01 1 1.E+01 1.E+02 E 02 1.E+03 1 1k E 03 1.E+04 1 10k E 04 1 1.E+05 E 05 Frequency (Hz) 100 90 80 70 60 50 40 30 20 10 0 1 kHz tone VDD = 5.5V VDD = 2.3V 10 1 GDM = 1 V/V VDD tone = 50 mVP-P, f = 1 kHz 0.
PAGE 16
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. Time Response 2 0 -2 90 80 70 60 VOS -4 -6 -8 -10 100 50 40 30 20 TPCB -12 10 -14 0 20 40 60 0 80 100 120 140 160 180 Time (s) 0 FIGURE 2-41: Input Offset Voltage vs. Time with Temperature Change.
PAGE 17
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, 6.0 VDD = 5.5V G = -1 5.0 5 G VIN VOUT 4.0 4 3.0 3 2.0 VDD = 5.5V G = -100 V/V 0.5V Overdrive 1.0 VOUT 2 G VIN 0.0 0 5 10 15 FIGURE 2-47: Response. 20 25 30 Time (µs) 35 40 45 Inverting Large Signal Step 1.4 Falling Edge 1.2 1.0 0.8 0.6 VDD = 2.3V Rising Edge 0.4 0.2 0.0 -50 -25 FIGURE 2-48: Temperature. 0 25 50 75 100 Ambient Temperature (°C) Slew Rate vs.
PAGE 18
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS = GND. 2.6 Chip Select Response (MCP6V28 only) 1.0 CS = VDD 0.9 Chip Select Current (μA) Chip Select Current (μA) 1.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-51: Chip Select Current vs. Power Supply Voltage. 0.0 0.5 1.
PAGE 19
MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS = GND. 7 65% Pull-down Resistor (M ) Relative Chip Select Logic Levels; Low and High (V/V) 70% VDD = 5.5V VIH/VDD 60% 55% 50% 45% 40% VDD = 2.3V VIL/VDD 35% -50 -25 0 25 50 75 100 Ambient Temperature (°C) 4 3 2 1 -50 125 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-60: Chip Select’s Pull-down Resistor (RPD) vs.
PAGE 20
MCP6V26/7/8 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1.
PAGE 21
MCP6V26/7/8 4.0 APPLICATIONS 4.1 The MCP6V26/7/8 family of auto-zeroed op amps are manufactured using Microchip’s state-of-the-art CMOS process. This family is designed for low cost, low power and high precision applications. Its low supply voltage, low quiescent current and wide bandwidth make the MCP6V26/7/8 devices ideal for battery-powered applications. Overview of Auto-Zeroing Operation Figure 4-1 shows a simplified diagram of the MCP6V26/7/8 auto-zeroed op amps.
PAGE 22
MCP6V26/7/8 4.1.2 AUTO-ZEROING ACTION Figure 4-2 shows the connections between amplifiers during the Normal Mode of operation (φ1). The hold capacitor (CH) corrects the Null Amplifier’s input offset. Since the Null Amplifier has very high gain, it dominates the signal seen by the Main Amplifier. This greatly reduces the impact of the Main Amplifier’s input offset voltage on overall performance.
PAGE 23
MCP6V26/7/8 4.2 Other Functional Blocks 4.2.1 RAIL-TO-RAIL INPUTS The input stage of the MCP6V26/7/8 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM, which is approximately equal to VIN+ and VIN– in normal operation) and the other at high VCM. With this topology, the input operates with VCM up to VDD + 0.2V, and down to VSS – 0.15V, at +25°C (see Figure 2-18). The input offset voltage (VOS) is measured at VCM = VSS – 0.15V and VDD + 0.
PAGE 24
MCP6V26/7/8 It is also possible to connect the diodes to the left of resistors R1 and R2. In this case, the currents through diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-17. 4.2.
PAGE 25
MCP6V26/7/8 4.3.6 CAPACITIVE LOADS 4.3.7 Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. These auto-zeroed op amps have a different output impedance than most op amps, due to their unique topology.
PAGE 26
MCP6V26/7/8 The largest value of RF that should be used depends on noise gain (see GN in Section 4.3.6, Capacitive Loads), CG and the open-loop gain’s phase shift. An approximate limit for RF is: EQUATION 4-2: 12 pF 2 R F ≤ 2 k Ω × --------------- × G N CG Some applications may modify these values to reduce either output loading or gain peaking (step response overshoot). At high gains, RG and CG need to be small in order to prevent positive feedback and oscillations. 4.3.
PAGE 27
MCP6V26/7/8 4.3.11.2 Crosstalk DC crosstalk causes offsets that appear as a larger input offset voltage. Common causes include: • Common mode noise (remote sensors) • Ground loops (current return paths) • Power supply coupling Interference from the mains (usually 50 Hz or 60 Hz), and other AC sources, can also affect the DC performance. Non-linear distortion can convert these signals to multiple tones, including a DC shift in voltage.
PAGE 28
MCP6V26/7/8 4.4.2 RTD SENSOR 4.4.3 The ratiometric circuit in Figure 4-14 conditions a three wire RTD. It corrects for the sensor’s wiring resistance by subtracting the voltage across the middle RW. The top R1 does not change the output voltage; it balances the op amp inputs. Failure (open) of the RTD is detected by an out-of-range voltage. U1A ½ MCP6V27 2.49 kΩ VDD RW 10 nF R1 2.49 kΩ 1 µF RRTD 100Ω 10 nF RW R1 2.49 kΩ RB 20 kΩ V1 ≈ THJ(40 µV/°C) R3 100 kΩ R2 2.55 kΩ V2 = (1.
PAGE 29
MCP6V26/7/8 The MCP9700A senses the temperature at its physical location. It needs to be at the same temperature as the cold junction (TCJ), and produces V3 (Figure 4-15). The MCP1541 produces a 4.10V output, assuming VDD is at 5.0V. This voltage, tied to a resistor ladder of 4.100(RTH) and 1.3224(RTH), would produce a Thevenin equivalent of 1.00V and 250(RTH). The 1.3224(RTH) resistor is combined in parallel with the top right RTH resistor (in Figure 4-15), producing the 0.5696(RTH) resistor.
PAGE 31
MCP6V26/7/8 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP6V26/7/8 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6V26/7/8 family of op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities.
PAGE 33
MCP6V26/7/8 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN (4x4x0.9 mm) (MCP6V27) Example XXXXXX XXXXXX YYWW NNN 6V27 E/MDe3 1129 256 PIN 1 PIN 1 8-Lead MSOP (3x3 mm) Example 6V27E 129256 8-Lead SOIC (3.90 mm) Example MCP6V27E SN^^ e3 1129 256 NNN 8-Lead TDFN (2x3x0.75 mm) (MCP6V26, MCP6V28) Device Legend: XX...
PAGE 34
MCP6V26/7/8 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 1 of 2 DS25007B-page 34 © 2011 Microchip Technology Inc.
PAGE 35
MCP6V26/7/8 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 2 of 2 © 2011 Microchip Technology Inc.
PAGE 36
MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 36 © 2011 Microchip Technology Inc.
PAGE 37
MCP6V26/7/8 1 % & % ! % 2 " ) ' % 2 $ % % " % %% 033))) & &3 2 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 4 % & 5 & % 6!&( $ 55 * * 6 6 67 8 9 % 7 ; % < < + 9+ + < + " " 2 2 % " $$ :+ . / 7 = "% * " " 2 = "% * , .
PAGE 38
MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 38 © 2011 Microchip Technology Inc.
PAGE 39
MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
PAGE 40
MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 40 © 2011 Microchip Technology Inc.
PAGE 42
MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 42 © 2011 Microchip Technology Inc.
PAGE 43
MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
PAGE 44
MCP6V26/7/8 + , " -.#.&$/0 ' ( 1+, 1 % & % ! % 2 " ) ' % 2 $ % % " % %% 033))) & &3 2 DS25007B-page 44 © 2011 Microchip Technology Inc.
PAGE 45
MCP6V26/7/8 APPENDIX A: REVISION HISTORY Revision B (August 2011) The following is the list of modifications: 1. 2. 3. 4. Added the MCP6V26 and MCP6V28 single op amps. a) Updated package drawings on page 1. b) Updated the pinout table (Table 3-1). c) Added 8-lead, 2×3 TDFN package to the Thermal Characteristics Table (Table 1-4). d) Added 8-lead, 2×3 TDFN package to Section 6.0 “Packaging Information”. e) Added parts numbers to Product Identification System. Added Chip Select (CS) information.
PAGE 46
MCP6V26/7/8 APPENDIX B: OFFSET RELATED TEST SCREENS We use production screens to ensure the quality of our outgoing products. These screens are set at wider limits to eliminate any fliers; see Table B-1. Input offset voltage-related specifications in the DC spec table (Table 1-1) are based on bench measurements (see Section 2.1 “DC Input Precision”).
PAGE 47
MCP6V26/7/8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 49
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 50
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