Datasheet

MCP6V11/1U
DS25124A-page 6 © 2012 Microchip Technology Inc.
1.3 Timing Diagrams
FIGURE 1-1: Amplifier Start Up.
FIGURE 1-2: Offset Correction Settling
Time.
FIGURE 1-3: Output Overdrive Recovery.
1.4 Test Circuits
The circuits used for most DC and AC tests are shown
in Figure 1-4 and Figure 1-5. Lay the bypass capacitors
out as discussed in Section 4.3.10, Supply Bypassing
and Filtering. R
N
is equal to the parallel combination of
R
F
and R
G
to minimize bias current effects.
FIGURE 1-4: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-5: AC and DC Test Circuit for
Most Inverting Gain Conditions.
The circuit in Figure 1-6 tests the input’s dynamic
behavior (i.e., IMD, t
STR
, t
STL
and t
ODR
). The
potentiometer balances the resistor network (V
OUT
should equal V
REF
at DC). The op amp’s common
mode input voltage is V
CM
=V
IN
/2. The error at the
input (V
ERR
) appears at V
OUT
with a noise gain of
10 V/V.
FIGURE 1-6: Test Circuit for Dynamic
Input Behavior.
V
DD
V
OUT
1.001(V
DD
/3)
0.999(V
DD
/3)
t
STR
0V
1.6V to 5.5V
1.6V
V
IN
V
OS
V
OS
+100µV
V
OS
–100µV
t
STL
V
IN
V
OUT
V
DD
V
SS
t
ODR
t
ODR
V
DD
/2
V
DD
R
G
R
F
R
N
V
OUT
V
IN
V
DD
/3
1µF
C
L
R
L
V
L
100 nF
R
ISO
MCP6V1X
V
DD
R
G
R
F
R
N
V
OUT
V
DD
/3
V
IN
1µF
C
L
R
L
V
L
100 nF
R
ISO
MCP6V1X
V
DD
V
OUT
1µF
C
L
V
L
R
ISO
11.0 kΩ
249 Ω
11.0 kΩ 500 Ω
V
IN
V
REF
=V
DD
/3
0.1%
0.1% 25 turn
100 kΩ
100 kΩ
0.1%
0.1%
R
L
0 Ω
20 pF open
100 nF
1%
MCP6V1X