Datasheet

MCP6V11/1U
DS25124A-page 22 © 2012 Microchip Technology Inc.
4.3.4 SOURCE RESISTANCES
The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10 Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.
4.3.5 SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match. Large
input capacitances and source resistances, together
with high gain, can lead to positive feedback and
instability.
4.3.6 CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These zero-drift op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
series resistor at the output (R
ISO
in Figure 4-7)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
FIGURE 4-7: Output Resistor, R
ISO
,
Stabilizes Capacitive Loads.
Figure 4-8 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
load capacitance (C
L
). The y-axis is the resistance
(R
ISO
).
G
N
is the circuit’s noise gain. For non-inverting gains,
G
N
and the Signal Gain are equal. For inverting gains,
G
N
is 1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
FIGURE 4-8: Recommended R
ISO
Values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
's value until the
response is reasonable. Bench evaluation is helpful.
4.3.7 STABILIZING OUTPUT LOADS
This family of zero-drift op amps has an output
impedance (Figure 2-31 and Figure 2-32) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low
impedance near the part’s bandwidth. This large phase
shift can cause stability problems.
Figure 4-9 shows that the load on the output is
(R
L
+R
ISO
)||(R
F
+R
G
), where R
ISO
is before the load
(like Figure 4-7). This load needs to be large enough to
maintain performance; it should be at least 10 kΩ.
FIGURE 4-9: Output Load.
R
ISO
C
L
V
OUT
U
1
MCP6V1X
1E+03
1.E+04
1.E+05
m
mended R
ISO
()
R
L
||(R
F
+ R
G
)  100 k
100k
10k
1k
1.E+02
1
.
E+03
1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Reco
m
Capacitive Load (F)
G
N
= 1 G
N
= 10 G
N
= 100
100
1k
10p 100p 1n 10n 100n 1μ
R
G
R
F
V
OUT
U
1
MCP6V1X
R
L
C
L