Datasheet

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MCP6V11/1U

Features

• High DC Precision:

-V

Drift: ±50 nV/°C (maximum)

-V

: ±8 µV (maximum)

-A

: 112 dB (minimum, V

=5.5V)

- PSRR: 118 dB (minimum, V

=5.5V)

- CMRR: 119 dB (minimum, V

=5.5V)

-E

: 2.1 µV

P-P

(typical), f = 0.1 Hz to 10 Hz

-E

: 0.67 µV

P-P

(typical), f = 0.01 Hz to 1 Hz

• Low Power and Supply Voltages:

-I

: 7.5 µA/amplifier (typical)

- Wide Supply Voltage Range: 1.6V to 5.5V

• Small Packages

- Singles in SC70, SOT-23

•Easy to Use:

- Rail-to-Rail Input/Output

- Gain Bandwidth Product: 80 kHz (typical)

- Unity Gain Stable

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• Portable Instrumentation

• Sensor Conditioning

• Temperature Measurement

• DC Offset Correction

• Medical Instrumentation

Design Aids

• SPICE Macro Models

•FilterLab

Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Related Parts

• MCP6V01/2/3: Auto-Zeroed, Spread Clock

• MCP6V06/7/8: Auto-Zeroed

• MCP6V26/7/8: Auto-Zeroed, Low Noise

• MCP6V31/1U: Zero-Drift, Low Power

Description

The Microchip Technology Inc. MCP6V11/1U family of

operational amplifiers provides input offset voltage

correction for very low offset and offset drift. These are

low power devices, with a gain bandwidth product of

80 kHz (typical). They are unity gain stable, have no 1/f

noise, and have good Power Supply Rejection Ratio

(PSRR) and Common Mode Rejection Ratio (CMRR).

These products operate with a single supply voltage as

low as 1.6V, while drawing 7.5 µA/amplifier (typical) of

quiescent current.

The Microchip Technology Inc. MCP6V11/1U op amps

are offered in single (MCP6V11 and MCP6V11U)

packages. They were designed using an advanced

CMOS process.

Package Types

Typical Application Circuit

–

OUT

MCP6V11

SOT-23

MCP6V11U

SC70, SOT-23

–

OUT

MCP6XXX

Offset Voltage Correction for Power Driver

OUT

MCP6V11

7.5 µA, 80 kHz Zero-Drift Op Amps

Summary of content (40 pages)

PAGE 1
MCP6V11/1U 7.5 µA, 80 kHz Zero-Drift Op Amps Features Description • High DC Precision: - VOS Drift: ±50 nV/°C (maximum) - VOS: ±8 µV (maximum) - AOL: 112 dB (minimum, VDD = 5.5V) - PSRR: 118 dB (minimum, VDD = 5.5V) - CMRR: 119 dB (minimum, VDD = 5.5V) - Eni: 2.1 µVP-P (typical), f = 0.1 Hz to 10 Hz - Eni: 0.67 µVP-P (typical), f = 0.01 Hz to 1 Hz • Low Power and Supply Voltages: - IQ: 7.5 µA/amplifier (typical) - Wide Supply Voltage Range: 1.6V to 5.
PAGE 3
MCP6V11/1U 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † VDD – VSS .................................................................................................................................................................6.5V Current at Input Pins ..............................................................................................................................................±2 mA Analog Inputs (VIN+ and VIN–) (Note 1) ..................................................
PAGE 4
MCP6V11/1U TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to +5.5V, VSS = GND, VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5). Parameters Sym. Min. Typ. Max. Units Conditions Common-Mode Input Voltage Range Low VCML — — VSS − 0.15 V (Note 2) Common-Mode Input Voltage Range High VCMH VDD + 0.
PAGE 5
MCP6V11/1U TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5). Parameters Sym. Min. Typ. Max. Units Conditions GBWP — 80 — kHz Slew Rate SR — 0.03 — V/µs Phase Margin PM — 70 — ° Eni — 0.67 — µVP-P f = 0.01 Hz to 1 Hz µVP-P f = 0.
PAGE 6
MCP6V11/1U 1.3 Timing Diagrams 1.4 1.6V to 5.5V 1.6V VDD 0V tSTR 1.001(VDD/3) VOUT Test Circuits The circuits used for most DC and AC tests are shown in Figure 1-4 and Figure 1-5. Lay the bypass capacitors out as discussed in Section 4.3.10, Supply Bypassing and Filtering. RN is equal to the parallel combination of RF and RG to minimize bias current effects. 0.999(VDD/3) FIGURE 1-1: Amplifier Start Up.
PAGE 7
MCP6V11/1U 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 8
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. 45% VDD = 1.6V Representative Part 6 Pe ercenta age of Occurrrences s Input O Offset V Voltage e (μV) 8 4 2 0 -2 -40°C 40°C +25°C +85°C +125°C -4 -6 -8 -0.5 30% 25% 20% 15% 10% 5% 2.5 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1/PSRR (μV/V) FIGURE 2-10: 45% 8 VDD = 5.
PAGE 9
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. 10000 10n Input Bias s, Offse et Currrents (A A) 160 DC Ope D en-Loo op Gain n (dB) 155 150 145 VDD = 5.5V VDD = 1.6V 140 135 130 125 120 115 110 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 IOS 10 10p IB 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) 1.E-02 10m 1.E-03 1.
PAGE 10
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Other DC Voltages and Currents 6.5 6.0 5.5 10 VDD – VOH 100 VDD = 5.5V VDD = 1.6V VOL – VSS 10 Supply C Current (μA/amplifier) 9 8 7 6 5 4 +125°C +85°C +25°C -40°C 3 2 1 5.5 5.0 4.5 4.0 Power Supply Voltage (V) FIGURE 2-19: Output Voltage Headroom vs. Output Current. FIGURE 2-22: Supply Voltage. Supply Current vs.
PAGE 11
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. 1.6 POR R Trip Voltage (V) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-24: Power-on Reset Voltage vs. Ambient Temperature. © 2012 Microchip Technology Inc.
PAGE 12
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Frequency Response Gain Band dwidth Product (kHz) 140 90 70 60 CMRR PSRR 20 10 60 60 40 50 VDD = 1.6V GBWP 20 40 1k 10k 100k 1.E+03 1.E+04 1.E+05 Frequency (Hz) -270 1M 1.E+06 -30 50 -60 40 -90 30 AOL -120 20 -150 10 180 -180 | AOL | 0 -10 -210 -240 1k 10k 100k 1.E+03 1.E+04 1.E+05 Frequency (Hz) -270 1M 1.
PAGE 13
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. 10 VDD = 1.6V Max ximum Outputt Voltag ge Swiing (VP--P) Closed-Loo op Output Impedance ( ) 1.E+05 100k 1.E+04 10k 1.E+03 1k 1.E+02 100 1.E+01 10 G = 1 V/V G = 11 V/V G = 101 V/V 1.E+001 100 1.E+02 Closed-Loo op Output Impedance ( ) 1 1.E+02 VDD = 1.6V 1.E+03 1.E+04 1.E+05 01 0.1 1k 1.E+03 100k 10k 1.E+04 1.E+05 Frequency (Hz) 1M 1.
PAGE 14
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Input Noise and Distortion 1000 1000 eni 100 100 VDD = 5.5V VDD = 1.6V 10 10 Eni(0 Hz to f) GDM = 1 V/V VDD tone = 50 mVPK, f = 100 Hz IMD Sp pectrum m, RTI ((μVPK) Input No oise Voltage Density; eni (nV/¥Hz) 1000 Integrated d Input Noise Voltage; Eni (μVP-P) 2.4 100 IMD tone at DC 100 Hz tone 10 1 1 1 10 1.E+02 100 1.E+03 1k 1.
PAGE 15
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Time Response 80 80 35 60 70 TPCB 30 40 25 20 VDD = 1.6V VDD = 5.5V 20 0 15 -20 10 -40 VOS 5 -60 0 -80 Temperature increased by using heat gun for 5 seconds. -5 -120 Input O Offset Voltage (mV) 30 20 0 0 VDD 6 5 6 5.5 5 5.
PAGE 16
MCP6V11/1U Note: Unless otherwise indicated, TA = +25°C, VDD = +1.6V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. VDD = 5.5V G = -1 5.0 7 7 6 6 Input Voltage × G (1 V/div) 5.5 Outp put Voltage (V) Outtput Voltage (V) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 5 VOUT G VIN 4 4 3 3 2 2 VDD = 5 5.5V 5V G = -10 V/V 0.5V Overdrive 1 G VIN 1 VOUT 0 0.5 0.0 FIGURE 2-46: Response. Inverting Large Signal Step 0 -1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.
PAGE 17
MCP6V11/1U 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: 3.1 PIN FUNCTION TABLE MCP6V11 MCP6V11U SOT-23 SOT-23, SC-70 1 4 VOUT 2 2 VSS 3 1 VIN+ Non-inverting Input (op amp A) 4 3 VIN– Inverting Input (op amp A) 5 5 VDD Positive Power Supply Symbol Description Output (op amp A) Negative Power Supply Analog Outputs The analog output pins (VOUT) are low-impedance voltage sources. 3.
PAGE 19
MCP6V11/1U 4.0 APPLICATIONS The MCP6V11/1U family of zero-drift op amps is manufactured using Microchip’s state of the art CMOS process. It is designed for precision applications with requirements for small packages and low power. Its low supply voltage and low quiescent current make the MCP6V11/1U devices ideal for battery-powered applications. 4.1 Overview of Zero-Drift Operation Figure 4-1 shows a simplified diagram of the MCP6V11/1U zero-drift op amps.
PAGE 20
MCP6V11/1U 4.1.3 INTERMODULATION DISTORTION (IMD) These op amps will show intermodulation distortion (IMD) products when an AC signal is present. The signal and clock can be decomposed into sine wave tones (Fourier series components). These tones interact with the zero-drift circuitry’s non-linear response to produce IMD tones at sum and difference frequencies. Each of the square wave clock’s harmonics has a series of IMD tones centered on it. See Figure 2-36 and Figure 2-37. 4.2 4.2.
PAGE 21
MCP6V11/1U 4.2.1.3 Input Current Limits 4.3 In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see Section 1.1, Absolute Maximum Ratings †). This requirement is independent of the voltage limits discussed previously. Figure 4-6 shows one approach to protecting these inputs. The resistors R1 and R2 limit the possible current in or out of the input pins (and into D1 and D2). The diode currents will dump onto VDD.
PAGE 22
MCP6V11/1U SOURCE RESISTANCES The input bias currents have two significant components; switching glitches that dominate at room temperature and below, and input ESD diode leakage currents that dominate at +85°C and above. Make the resistances seen by the inputs small and equal. This minimizes the output offset caused by the input bias currents. The inputs should see a resistance on the order of 10 Ω to 1 kΩ at high frequencies (i.e., above 1 MHz).
PAGE 23
MCP6V11/1U 4.3.8 GAIN PEAKING 4.3.9 Figure 4-10 shows an op amp circuit that represents non-inverting amplifiers (VM is a DC voltage and VP is the input) or inverting amplifiers (VP is a DC voltage and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they include the op amp’s common mode input capacitance (CCM), board parasitic capacitance and any capacitor placed in parallel.
PAGE 24
MCP6V11/1U Typical thermojunctions have temperature to voltage conversion coefficients of 1 to 100 µV/°C (sometimes higher). 4.4 Microchip’s AN1258 (“Op Amp Precision Design: PCB Layout Techniques”) contains in-depth information on PCB layout techniques that minimize thermojunction effects. It also discusses other effects, such as crosstalk, impedances, mechanical stresses and humidity. Many sensors are configured as Wheatstone bridges. Strain gauges and pressure sensors are two common examples.
PAGE 25
MCP6V11/1U 4.4.3 OFFSET VOLTAGE CORRECTION Figure 4-13 shows MCP6V11 (U2) correcting the input offset voltage of another op amp (U1). R2 and C2 integrate the offset error seen at U1’s input; the integration needs to be slow enough to be stable (with the feedback provided by R1 and R3). R4 and R5 attenuate the integrator’s output; this shifts the integrator pole down in frequency. R1 VIN R3 R2 VOUT R4 C2 U1 R5 R2 VDD/2 MCP6XXX U2 VDD/2 MCP6V11 FIGURE 4-13: 4.4.4 Offset Correction.
PAGE 27
MCP6V11/1U 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP6V11/1U family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6V11/1U op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities.
PAGE 29
MCP6V11/1U 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SC70 (MCP6V11U) Device MCP6V11UT-E/LT Note: Code Applies to 5-Lead SC-70. Example: 5-Lead SOT-23 (MCP6V11/1U) Device e3 * Note: Code MCP6V11T-E/OT 2CNN MCP6V11UT-E/OT 2DNN Note: Legend: XX...X Y YY WW NNN DJ25 DJNN 2C25 Applies to 5-Lead SOT-23.
PAGE 30
MCP6V11/1U /HDG 3ODVWLF 6PDOO 2XWOLQH 7UDQVLVWRU /7 >6& @ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D b 3 1 2 E1 E 4 e A e 5 A2 c A1 L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ ± 6WDQGRII $ ± 2YHUDOO :LGWK ( 0ROGHG 3DFNDJH :LGWK (
PAGE 31
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PAGE 32
MCP6V11/1U /HDG 3ODVWLF 6PDOO 2XWOLQH 7UDQVLVWRU 27 >627 @ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ b N E E1 3 2 1 e e1 D A2 A c φ A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 120 0$; 1 /HDG 3LWFK H %6& 2XWVLGH /HDG 3LWFK H 2YHUDOO +HLJKW $ ± 0ROGHG 3DFNDJH 7KLFNQHVV $ ± 6WDQGRII $ ± 2YHUDOO :LGWK ( ±
PAGE 33
MCP6V11/1U Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2012 Microchip Technology Inc.
PAGE 35
MCP6V11/1U APPENDIX A: REVISION HISTORY Revision A (March 2012) • Original Release of this Document. © 2012 Microchip Technology Inc.
PAGE 37
MCP6V11/1U PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 39
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 40
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