Datasheet

 2004 Microchip Technology Inc. DS21908A-page 8
MCP6S91/2/3
FIGURE 1-5: Detailed SPI™ Serial Interface Timing; SPI 1,1 Mode.
1.1 DC Output Voltage Specs / Model
1.1.1 IDEAL MODEL
The ideal PGA output voltage (V
OUT
) is:
EQUATION 1-1:
(see Figure 1-6). This equation holds when there are
no gain or offset errors and when the V
REF
pin is tied to
a low-impedance source (<< 0.1Ω) at ground potential
(V
SS
= 0V).
1.1.2 LINEAR MODEL
The PGA’s linear region of operation, including offset
and gain errors, is modeled by the line V
O_LIN
shown in
Figure 1-6.
EQUATION 1-2:
The end points of this line are at V
O_ID
= 0.3V and
V
DD
– 0.3V. Figure 1-6 shows the relationship between
the gain and offset specifications referred to in the
electrical specifications as follows:
EQUATION 1-3:
The DC Gain Drift (∆G/∆T
A
) can be calculated from the
change in g
E
across temperature. This is shown in the
following equation:
EQUATION 1-4:
CS
SCK
SI
t
SU
t
HD
t
CSSC
t
SCCS
SO
(first 16 bits out are always zeros)
t
DO
t
SOZ
t
HI
t
LO
1/f
SCK
t
CS1
t
CSH
t
CS0
Where:
G is the nominal gain
V
O_ID
G
VIN
= V
REF
V
SS
0V==
V
O_LIN
G1 g
E
+()V
IN
0.3V
G
-----------
V
OS
+–


0.3V+=
V
REF
V
SS
0V==
g
E
100%
V
2
V
1
–
GV
DD
0.6V–()
--------------------------------------
=
V
OS
V
1
G1 g
E
+()
-------------------------
= G+1=
G∆ T
A
∆⁄
g
E
∆
T
A
∆
----------
=