Datasheet

 2004 Microchip Technology Inc. DS21908A-page 5
MCP6S91/2/3
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T
A
= 25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R
L
=10kΩ to V
DD
/2, C
L
= 60 pF, SI and SCK are tied low and CS is tied high.
Parameters Sym Min Typ Max Units Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low V
IL
0 — 0.3V
DD
V
Input Leakage Current I
IL
-1.0 — +1.0 µA
Logic Threshold, High V
IH
0.7 V
DD
—V
DD
V
Amplifier Output Leakage Current — -1.0 — 1.0 µA In Shutdown mode
SPI Output (SO, for MCP6S93)
Logic Threshold, Low V
OL_DIG
V
SS
—V
SS
+0.4 V I
OL
= 2.1 mA, V
DD
= 5V
Logic Threshold, High V
OH_DIG
V
DD
– 0.5 — V
DD
VI
OH
= -400 µA
SPI Timing
Pin Capacitance C
PIN
— 10 — pF All digital I/O pins
Input Rise/Fall Times (CS
, SI, SCK) t
RFI
——2µs(Note 1)
Output Rise/Fall Times (SO) t
RFO
—5—nsMCP6S93
CS
High Time t
CSH
40 — — ns
SCK Edge to CS
Fall Setup Time t
CS0
10 — — ns SCK edge when CS is high
CS
Fall to First SCK Edge Setup Time t
CSSC
40 — — ns
SCK Frequency f
SCK
——10MHzV
DD
= 5V (Note 2)
SCK High Time t
HI
40 — — ns
SCK Low Time t
LO
40 — — ns
SCK Last Edge to CS
Rise Setup Time t
SCCS
30 — — ns
CS
Rise to SCK Edge Setup Time t
CS1
100 — — ns SCK edge when CS is high
SI Setup Time t
SU
40 — — ns
SI Hold Time t
HD
10 — — ns
SCK to SO Valid Propagation Delay t
DO
— — 80 ns MCP6S93
CS
Rise to SO Forced to Zero t
SOZ
— — 80 ns MCP6S93
Channel and Gain Select Timing
Channel Select Time t
CH
— 1.5 — µs CHx = 0.6V, CHy = 0.3V, G = 1,
CHx to CHy select,
CS
= 0.7 V
DD
to V
OUT
90% point
Gain Select Time t
G
— 1 — µs CHx = CHy = 0.3V,
G = 5 to G = 1 select,
CS
= 0.7 V
DD
to V
OUT
90% point
Shutdown Mode Timing
Out of Shutdown mode (CS
goes high)
to Amplifier Output Turn-on Time
t
ON
—3.510µsCS = 0.7 V
DD
to V
OUT
90% point
Into Shutdown mode (CS
goes high) to
Amplifier Output High-Z Turn-off Time
t
OFF
—1.5—µsCS = 0.7 V
DD
to V
OUT
90% point
Note 1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t
DO
≤ 80 ns), data input set-up time (t
SU
≥ 40 ns), SCK high time (t
HI
≥ 40 ns) and SCK rise and
fall times of 5 ns. Maximum f
SCK
is therefore ≈ 5.8 MHz.