Datasheet

 2004 Microchip Technology Inc. DS21908A-page 21
MCP6S91/2/3
5.0 DIGITAL FUNCTIONS
The MCP6S91/2/3 PGAs use a standard SPI
compatible serial interface to receive instructions from
a controller. This interface is configured to allow daisy-
chaining with other SPI devices.
5.1 SPI Timing
Chip Select (CS) toggles low to initiate communica-
tion with these devices. The first byte of each SI word
(two bytes long) is the instruction byte, which goes
into the Instruction register. The Instruction register
points the second byte to its destination. In a typical
application, CS
is raised after one word (16 bits) to
implement the desired changes. Section 5.3 “Daisy-
Chain Configuration”, covers applications using
multiple 16-bit words. SO goes low after CS
goes
high; it has a push-pull output that does not go into a
high-Z state.
The MCP6S91/2/3 devices operate in SPI modes 0,0
and 1,1. In 0,0 mode, the clock idles in the low state
(Figure 5-1). In 1,1 mode, the clock idles in the high
state (Figure 5-2). In both modes, SI data is loaded into
the PGA on the rising edge of SCK, while SO data is
clocked out on the falling edge of SCK. In 0,0 mode, the
falling edge of CS
also acts as the first falling edge of
SCK (see Figure 5-1). There must be multiples of 16
clocks (SCK) while CS is low or commands will abort
(see Section 5.3 “Daisy-Chain Configuration”).
FIGURE 5-1: Serial Bus Sequence for the PGA; SPI™ 0,0 Mode (see Figure 1-4).
FIGURE 5-2: Serial Bus Sequence for the PGA; SPI™ 1,1 Mode (see Figure 1-5).
12345678910 11 12 13 14 15 16
bit 7
CS
SCK
SI
Instruction Byte Data Byte
bit 0
bit 7 bit 0
SO
(first 16 bits out are always zeros)
12345678910 11 12 13 14 15 16
bit 7
CS
SCK
SI
Instruction Byte Data Byte
bit 0 bit 7 bit 0
SO
(first 16 bits out are always zeros)