Datasheet

 2004 Microchip Technology Inc. DS21908A-page 20
MCP6S91/2/3
4.4 Rail-to-Rail V
REF
Input
The V
REF
input is intended to be driven by a low-
impedance voltage source. The source driving the
V
REF
pin should have an output impedance less than
0.1Ω to maintain reasonable gain accuracy. The supply
voltage V
SS
and V
DD
usually meet this requirement.
R
LAD
presents a load at the V
REF
pin to the external
circuit (Z
IN_REF
≈ (5 kΩ/G)||(6 pF)), which depends on
the gain. Any source driving the V
REF
pin must be
capable of driving a load as heavy as 0.16 kΩ||6 pF
(G = 32).
The absolute maximum voltages that can be applied to
the reference input pin (V
REF
) are V
SS
–0.3V and
V
DD
+ 0.3V. Voltages on the inputs that exceed this
absolute maximum rating can cause excessive current
to flow into or out of this pin. Current beyond ±2 mA can
cause possible reliability problems. Because an
external series resistor cannot be used (for low gain
error), the external circuit must ensure that V
REF
is
between V
SS
– 0.3V and V
DD
+0.3V.
The V
IVR_REF
spec shows the region of normal
operation for the V
REF
pin (V
SS
to V
DD
). Staying within
this region ensures proper operation of the PGA and its
surrounding circuitry.
4.5 Shutdown Mode
These PGAs use a software shutdown command.
When the SPI interface sends a shutdown command,
the internal op amp is shut down and its output placed
in a High-Z state.
The resistive ladder is always connected between
V
REF
and V
OUT
; even in shutdown. This means that the
output resistance will be on the order of 5 kΩ, with a
path for output signals to appear at the input.