Datasheet

 2004 Microchip Technology Inc. DS21908A-page 2
MCP6S91/2/3
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
DD
–V
SS
........................................................................7.0V
All inputs and outputs..................... V
SS
–0.3VtoV
DD
+0.3V
Difference Input voltage ....................................... |V
DD
–V
SS
|
Output Short Circuit Current ..................................continuous
Current at Input Pin .............................................................±2mA
Current at Output and Supply Pins................................ ±30 mA
Storage temperature .....................................-65°C to +150°C
Junction temperature ..................................................+150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 200V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
PIN FUNCTION TABLE
Name Function
V
OUT
Analog Output
CH0, CH1 Analog Inputs
V
REF
External Reference Pin
V
SS
Negative Power Supply
CS
SPI Chip Select
SI SPI Serial Data Input
SO SPI Serial Data Output
SCK SPI Clock Input
V
DD
Positive Power Supply
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, R
L
=10kΩ to V
DD
/2, SI and SCK are tied low and CS is tied high.
Parameters Sym Min Typ Max Units Conditions
Amplifier Inputs (CH0, CH1)
Input Offset Voltage V
OS
-4 — +4 mV G = +1
Input Offset Voltage Mismatch ∆V
OS
— 0 — µV Between inputs (CH0, CH1)
Input Offset Voltage Drift ∆V
OS
/∆T
A
—±1.8 — µV/°CT
A
= -40°C to +125°C
Power Supply Rejection Ratio PSRR 70 90 — dB G = +1 (Note 1)
Input Bias Current I
B
— ±1 — pA CHx = V
DD
/2
Input Bias Current at
Temperature
I
B
— 30 — pA CHx = V
DD
/2, T
A
= +85°C
I
B
— 600 — pA CHx = V
DD
/2, T
A
= +125°C
Input Impedance Z
IN
—10
13
||7 — Ω||pF
Input Voltage Range V
IVR
V
SS
− 0.3 — V
DD
+ 0.3 V (Note 2)
Reference Input (V
REF
)
Input Impedance Z
IN_REF
— (5/G)||6 — kΩ||pF
Voltage Range V
IVR_REF
V
SS
—V
DD
V (Note 2)
Amplifier Gain
Nominal Gains G — 1 to 32 — V/V +1, +2, +4, +5, +8, +10, +16 or +32
DC Gain Error G = +1 g
E
-0.2 — +0.2 % V
OUT
≈ 0.3V to V
DD
− 0.3V
G ≥ +2 g
E
-1.0 — +1.0 % V
OUT
≈ 0.3V to V
DD
− 0.3V
DC Gain Drift G = +1 ∆G/∆T
A
— ±0.0002 — %/°C T
A
= -40°C to +125°C
G ≥ +2 ∆G/∆T
A
— ±0.0004 — %/°C T
A
= -40°C to +125°C
Note 1: R
LAD
(R
F
+R
G
in Figure 4-1) connects V
REF
, V
OUT
and the inverting input of the internal amplifier. The MCP6S92 has
V
REF
tied internally to V
SS
, so V
SS
is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is
recommended that the MCP6S92’s V
SS
pin be tied directly to ground to avoid noise problems.
2: The MCP6S92’s V
IVR
and V
IVR_REF
are not tested in production; they are set by design and characterization.
3: I
Q
includes current in R
LAD
(typically 60 µA at V
OUT
= 0.3V). Both I
Q
and I
Q_SHDN
exclude digital switching currents.