Datasheet

 2004 Microchip Technology Inc. DS21908A-page 18
MCP6S91/2/3
4.0 ANALOG FUNCTIONS
The MCP6S91/2/3 family of Programmable Gain
Amplifiers (PGA) is based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following subsections.
FIGURE 4-1: PGA Block Diagram.
4.1 Input MUX
The MCP6S91 has one input, while the MCP6S92 and
MCP6S93 have two inputs (see Figure 4-1).
For the lowest input current, float unused inputs. Tying
these pins to a voltage near the active channel’s bias
voltage also works well. For simplicity, they can be tied
to V
SS
or V
DD
, but the input current may increase.
The one-channel MCP6S91 has approximately the
same input bias current as the two-channel MCP6S92
and MCP6S93.
The input offset voltage mismatch between channels
(∆V
OS
) is, ideally, 0 µV. The input MUX uses CMOS
transmission gates that have drain-source (channel)
resistance, but no offset voltage. The histogram in
Figure 2-8 reflects the measurement repeatability
(i.e., noise power bandwidth) rather than the actual
mismatch. Reducing the measurement bandwidth will
produce a more narrow histogram and give an aver-
age closer to 0 µV.
4.2 Internal Op Amp
The internal op amp gives the right combination of
bandwidth, accuracy and flexibility.
4.2.1 COMPENSATION CAPACITORS
The internal op amp has three compensation capaci-
tors (comp. caps.) connected to a switching network.
They are selected to give good small-signal bandwidth
at high gains and good slew rates (full-power band-
width) at low gains. The change in bandwidth as gain
changes is between 2 and 12 MHz. Refer to Table 4-1
for more information.
TABLE 4-1: GAIN VS. INTERNAL
COMPENSATION
CAPACITOR
4.2.2 RAIL-TO-RAIL CHANNEL INPUTS
The input stage of the internal op amp uses two differ-
ential input stages in parallel; one operates at low V
IN
(input voltage), while the other operates at high V
IN
.
With this topology, the internal inputs can operate to
0.3V past either supply rail. The input offset voltage is
measured at both V
IN
=V
SS
– 0.3V and V
DD
+ 0.3V to
ensure proper operation.
The transition between the two input stages occurs
when V
IN
≈ V
DD
– 1.5V. For the best distortion and gain
linearity, avoid this region of operation.
MCP6S91 – One input (CH0), no SO pin
MCP6S92 – Two inputs (CH0, CH1), V
REF
tied
internally to V
SS
, no SO pin
MCP6S93 – Two inputs (CH0, CH1)
V
OUT
V
REF
V
DD
CS
SI
SO
SCK
CH1
CH0
V
SS
8
R
F
R
G
MUX
SPI™
Logic
Gain
Switches
Resistor Ladder (R
LAD
)
Gain
(V/V)
Internal
Comp.
Cap.
GBWP
(MHz)
Typ.
SR
(V/µs)
Typ.
FPBW
(MHz)
Typ.
BW
(MHz)
Typ.
1 Large 12 4.0 0.30 12
2 Large 12 4.0 0.30 6
4Medium 20 11 0.70 10
5Medium 20 11 0.70 7
8 Medium 20 11 0.70 2.4
10 Medium 20 11 0.70 2.0
16 Small 64 22 1.6 5
32 Small 64 22 1.6 2.0
Note 1: FPBW is the Full-Power Bandwidth.
These numbers are based on V
DD
=5.0V.
2: No changes in DC performance
(e.g., V
OS
) accompany a change in
compensation capacitor.
3: BW is the closed-loop, small signal -3 dB
bandwidth.