MCP6S21/2/6/8 Single-Ended, Rail-to-Rail I/O, Low Gain PGA Features Description • Multiplexed Inputs: 1, 2, 6 or 8 channels • 8 Gain Selections: - +1, +2, +4, +5, +8, +10, +16 or +32 V/V • Serial Peripheral Interface (SPI) • Rail-to-Rail Input and Output • Low Gain Error: ±1% (max) • Low Offset: ±275 µV (max) • High Bandwidth: 2 to 12 MHz (typ) • Low Noise: 10 nV/Hz @ 10 kHz (typ) • Low Supply Current: 1.0 mA (typ) • Single Supply: 2.5V to 5.5V The Microchip Technology Inc.
MCP6S21/2/6/8 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name Absolute Maximum Ratings † VDD - VSS .........................................................................7.0V Function VOUT Analog Output CH0-CH7 Analog Inputs All inputs and outputs ....................... VSS - 0.3V to VDD +0.3V VSS Negative Power Supply Difference Input voltage ........................................ |VDD - VSS| VDD Positive Power Supply Output Short Circuit Current..................................
MCP6S21/2/6/8 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, SI and SCK are tied low and CS is tied high. Parameters Sym Min Typ Max Units Conditions VDD 2.5 — 5.5 V IQ 0.5 1.0 1.35 mA IO = 0 (Note 2) IQ_SHDN — 0.5 1.0 µA IO = 0 (Note 2) VPOR 1.2 1.7 2.2 V (Note 3) VPOR/T — -3.
MCP6S21/2/6/8 DIGITAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high. Parameters Sym Min Typ Max Units Conditions SPI Inputs (CS, SI, SCK) Logic Threshold, Low VIL 0 — 0.3VDD V Input Leakage Current IIL -1.0 — +1.0 µA Logic Threshold, High VIH 0.
MCP6S21/2/6/8 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND.
MCP6S21/2/6/8 tCSH CS tCSSC tSCCS tCS1 tCS0 tLO tHI SCK tSU tHD 1/fSCK SI tDO tSOZ SO (first 16 bits out are always zeros) FIGURE 1-5: Detailed SPI Serial Interface Timing, SPI 0,0 mode. tCSH CS tCSSC tSCCS tCS1 tHI tCS0 tLO SCK tSU tHD 1/fSCK SI tDO tSOZ SO (first 16 bits out are always zeros) FIGURE 1-6: DS21117B-page 6 Detailed SPI Serial Interface Timing, SPI 1,1 mode. 2003-2012 Microchip Technology Inc.
MCP6S21/2/6/8 1.1 DC Output Voltage Specs / Model 1.1.1 VOUT (V) IDEAL MODEL The ideal PGA output voltage (VOUT) is: EQUATION V2 VDD-0.3 VREF = V SS = 0V O UT O _l in V ear O _i de al V O_ideal = GV IN VDD V V where: G is the nominal gain (see Figure 1-7). This equation holds when there are no gain or offset errors and when the VREF pin is tied to a low impedance source (<< 0.1) at ground potential (VSS = 0V). 1.1.2 V1 0.3 0 VIN (V) LINEAR MODEL 0 0.3 G VDD - 0.
MCP6S21/2/6/8 1.1.4 DIFFERENT VREF CONDITIONS Some of the plots in Section 2.0, “Typical Performance Curves”, have the conditions VREF = VDD/2 or VREF = VDD. The equations and figures above are easily modified for these conditions. The ideal VOUT becomes: EQUATION V O_ideal = VREF + G V IN – VREF V DD VREF VSS = 0V The complete linear model is: EQUATION V O_linear = G 1 + g E V IN – V IN_L + V OS + 0.3V where the new VIN endpoints are: EQUATION 0.
MCP6S21/2/6/8 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
MCP6S21/2/6/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, and CL = 60 pF. 22% G = +1 Percentage of Occurrences 150 100 50 0 VDD = +2.5 -50 -100 VDD = +5.5 -150 20% 18% 420 Samples TA = -40 to +125°C G = +1 16% 14% 12% 10% 8% 6% 4% 2% 5.0 5.5 VREF Voltage (V) FIGURE 2-7: VREF Voltage. FIGURE 2-10: 0.001 VONL/G, G = +2 VONL/G, G t +4 0.00001 8 6 4 0.0010% VONL/G, G t +2 3.
MCP6S21/2/6/8 100 120 Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, and CL = 60 pF. 110 100 90 80 70 -50 -25 0 25 50 75 100 90 80 VDD = 2.5 V 70 60 50 40 125 Input Referred VDD = 5.5 V 10 100 10 100 FIGURE 2-16: CH0 = VDD VDD = 5.5 V Input Bias Current (pA) Input Bias Current (pA) PSRR vs.
MCP6S21/2/6/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, and CL = 60 pF. 40 Gain (dB) 30 Quiescent Current (mA) G = +32 G = +16 20 10 0 G = +10 G = +8 G = +5 G = +4 -10 -20 G = +2 G = +1 1.E+05 1.E+06 100k 1.E+07 1M 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 1.E+08 10M 100M 0.0 0.5 1.
MCP6S21/2/6/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, and CL = 60 pF. 1 Measurement BW = 80 kHz VOUT = 2 VP-P VDD = 5.0 V THD + Noise (%) 0.1 G = +16 0.01 G = +4 Measurement BW = 80 kHz VOUT = 4 VP-P VDD = 5.0 V 0.1 G = +16 0.01 G = +4 G = +1 G = +1 0.001 100 0.001 100 1.E+02 1.E+02 1.E+03 1.E+04 1k 1.E+05 10k 100k 1.E+03 1.
MCP6S21/2/6/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = GND, VREF = VSS, G= +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, and CL = 60 pF. 1.0 20 0.8 15 0.7 10 0.6 5 CS CS 0.5 0 5 0 0.4 -5 0.3 -10 0.2 -15 VOUT is "ON" (CH0 = 0.3V, G = +1) 0.1 Output Voltage Swing (V P-P) Shutdown Chip Select Voltage (V) Output Voltage (mV) 10 25 Shutdown 0.9 VDD = 5.5 V VDD = 2.5 V 1 G = +1, +2 G = +4 to +10 G = +16, +32 -20 0.1 10k 1.E+04 0.
MCP6S21/2/6/8 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1.
MCP6S21/2/6/8 4.0 ANALOG FUNCTIONS 4.1 The MCP6S21/2/6/8 family of Programmable Gain Amplifiers (PGA) are based on simple analog building blocks (see Figure 4-1). Each of these blocks will be explained in more detail in the following sub-sections.
MCP6S21/2/6/8 4.2.2 RAIL-TO-RAIL INPUT 4.3 The input stage of the internal op amp uses two differential input stages in parallel; one operates at low VIN (input voltage), while the other operates at high VIN. With this topology, the internal inputs can operate to 0.3V past either supply rail. The input offset voltage is measured at both VIN = VSS - 0.3V and VDD + 0.3V to ensure proper operation. The transition between the two input stages occurs when VIN VDD - 1.5V.
MCP6S21/2/6/8 5.0 DIGITAL FUNCTIONS CS is raised after one word (16 bits) to implement the desired changes. Section 5.3, “Registers”, covers applications using multiple 16-bit words. SO goes low after CS goes high; it has a push-pull output that does not go into a high-Z state. The MCP6S21/2/6/8 PGAs use a standard SPI compatible serial interface to receive instructions from a controller. This interface is configured to allow daisy chaining with other SPI devices.
MCP6S21/2/6/8 5.2 Registers The analog functions are programmed through the SPI interface using 16-bit words (see Figure 5-1 and Figure 5-2). This data is sent to two of three 8-bit registers: Instruction Register (Register 5-1), Gain Register (Register 5-2) and Channel Register (Register 5-3).
MCP6S21/2/6/8 5.2.2 SETTING THE GAIN The amplifier can be programmed to produce binary and decimal gain settings between +1 V/V and +32 V/V. Register 5-2 shows the details. At the same time, different compensation capacitors are selected to optimize the bandwidth vs. slew rate trade-off (see Table 4-1).
MCP6S21/2/6/8 5.2.3 CHANGING THE CHANNEL If the instruction register is programmed to address the channel register, the multiplexed inputs of the MCP6S22, MCP6S26 and MCP6S28 can be changed per Register 5-3.
MCP6S21/2/6/8 5.2.4 SHUTDOWN COMMAND The example in Figure 5-3 shows a daisy chain configuration with two devices, although any number of devices can be configured this way. The MCP6S21 and MCP6S22 can only be used at the far end of the daisy chain because they do not have a serial data out (SO) pin. As shown in Figure 5-4 and Figure 5-5, both SI and SO data are sent in 16-bit (2 byte) words. These devices abort any command that is not a multiple of 16 bits.
MCP6S21/2/6/8 1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516 bit 7 bit 7 CS SCK Instruction Byte for Device 2 Instruction Byte for Device 1 Data Byte for Device 2 bit 0 bit 0 bit 7 bit 0 bit 0 bit 7 SI Data Byte for Device 1 Instruction Byte for Device 2 FIGURE 5-4: bit 0 bit 7 (first 16 bits out are always zeros) bit 0 bit 7 SO Data Byte for Device 2 Serial bus sequence for daisy-chain configuration; SPI 0,0 mode.
MCP6S21/2/6/8 5.4 Power-On Reset If the power supply voltage goes below the POR trip voltage (VDD < VPOR 1.7V), the internal POR circuit will reset all of the internal registers to their power-up defaults (this is a protection against low power supply voltages). The POR circuit also holds the part in shutdown mode while it is activated. It temporarily overrides the software shutdown status. The POR releases the shutdown circuitry once it is released (VDD > VPOR). A 0.
MCP6S21/2/6/8 6.0 APPLICATIONS INFORMATION 6.1 Changing External Reference Voltage Figure 6-1 shows a MCP6S21 with the VREF pin at 2.5V and VDD = 5.0V. This allows the PGA to amplify signals centered on 2.5V, instead of ground-referenced signals. The voltage reference MCP1525 is buffered by a MCP6021, which gives a low output impedance reference voltage from DC to high frequencies. The source driving the VREF pin should have an output impedance of 0.1 to maintain reasonable gain accuracy.
MCP6S21/2/6/8 6.4 Typical Applications 6.4.1 VIN GAIN RANGING MCP6021 Figure 6-3 shows a circuit that measures the current IX. It benefits from changing the gain on the PGA. Just as a hand-held multimeter uses different measurement ranges to obtain the best results, this circuit makes it easy to set a high gain for small signals and a low gain for large signals. As a result, the required dynamic range at the PGA’s output is less than at its input (by up to 30 dB). 10.0 k VOUT MCP6S21 1.
MCP6S21/2/6/8 6.4.5 6.4.7 EXPANDED INPUT PGA Figure 6-8 shows cascaded MCP6S28s that provide up to 15 input channels. Obviously, Sensors #7-14 have a high total gain range available, as explained in Section 6.4.3, “Extended Gain Range”. These devices can be daisy chained (Section 5.3, “Daisy Chain Configuration”). ADC DRIVER The family of PGA’s is well suited for driving Analog-toDigital Converters (ADC).
MCP6S21/2/6/8 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead PDIP (300 mil) (MCP6S21, MCP6S22) XXXXXXXX XXXXXNNN YYWW MCP6S21 I/P256 0345 8-Lead SOIC (150 mil) (MCP6S21, MCP6S22) XXXXXXXX XXXXYYWW NNN Note: * Example: MCP6S21I 345256 XXXXX YWWNNN XX...
MCP6S21/2/6/8 Package Marking Information (Con’t) 14-Lead PDIP (300 mil) (MCP6S26) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6S26) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) (MCP6S26) XXXXXXXX Example: MCP6S26-I/P XXXXXXXXXXXXXX 0345256 Example: MCP6S26ISL XXXXXXXXXXXXXXXXXXXXXXXXX 0345256 Example: MCP6S26IST YYWW 0345 NNN 256 2003-2012 Microchip Technology Inc.
MCP6S21/2/6/8 Package Marking Information (Con’t) 16-Lead PDIP (300 mil) (MCP6S28) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 16-Lead SOIC (150 mil) (MCP6S28) XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN DS21117B-page 30 MCP6S28-I/P XXXXXXXXXXXXXX 0345256 Example: MCP6S28-I/SL XXXXXXXXXXXXXXXXXXXXXXXX 0345256 2003-2012 Microchip Technology Inc.
MCP6S21/2/6/8 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
MCP6S21/2/6/8 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
MCP6S21/2/6/8 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E p E1 D 2 B n 1 A2 A c A1 (F) L INCHES Units Number of Pins Pitch Dimension Limits n p Overall Height MILLIMETERS* NOM MIN MAX NOM MIN .026 0.65 1.18 .044 A 0.86 0.97 4.67 4.90 .5.08 .122 2.90 3.00 3.10 .122 2.90 3.00 3.10 .022 .028 0.40 0.55 0.70 .
MCP6S21/2/6/8 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.
MCP6S21/2/6/8 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
MCP6S21/2/6/8 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
MCP6S21/2/6/8 16-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 16 .100 .155 .130 MAX MILLIMETERS NOM 16 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 .036 0.46 7.87 9.
MCP6S21/2/6/8 16-Lead Plastic Small Outline (SL) – Narrow 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
MCP6S21/2/6/8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Device Temperature Range Package Device: Examples: a) MCP6S21-I/P: One Channel PGA, PDIP package. b) MCP6S21-I/SN: One Channel PGA, SOIC package. c) MCP6S21-I/MS: One Channel PGA, MSOP package. d) MCP6S22-I/MS: Two Channel PGA, MSOP package. e) MCP6S22T-I/MS: Tape and Reel, Two Channel PGA, MSOP package.
MCP6S21/2/6/8 NOTES: DS21117B-page 40 2003-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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