Datasheet

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MCP6N11

FIGURE 4-9: Recommended R

ISO

Values

for Capacitive Loads.

After selecting R

ISO

for your circuit, double check the

resulting frequency response peaking and step

response overshoot on the bench. Modify R

ISO

’s value

until the response is reasonable.

4.3.3 GAIN RESISTORS

Figure 4-10 shows a simple gain circuit with the INA’s

input capacitances at the feedback inputs (V

REF

and

). These capacitances interact with R

and R

modify the gain at high frequencies. The equivalent

capacitance acting in parallel to R

is C

plus any board capacitance in parallel to R

. C

will

cause an increase in G

at high frequencies, which

reduces the phase margin of the feedback loop (i.e.,

reduce the feedback loop's stability).

FIGURE 4-10: Simple Gain Circuit with

Parasitic Capacitances.

In this data sheet, R

=10kΩ for most gains (0Ω

for G

= 1); see Table 1-6. This choice gives good

Phase Margin. In general, R

(Figure 4-10) needs to

meet the following limits to maintain stability:

EQUATION 4-12:

4.3.4 SUPPLY BYPASS

With these INAs, the power supply pin (V

for single

supply) should have a local bypass capacitor (i.e.,

0.01 µF to 0.1 µF) within 2 mm for good high frequency

performance. Surface mount, multilayer ceramic

capacitors, or their equivalent, should be used.

These INAs require a bulk capacitor (i.e., 1.0 µF or

larger) within 100 mm, to provide large, slow currents.

This bulk capacitor can be shared with other nearby

analog parts as long as crosstalk through the supplies

does not prove to be a problem.

1.E+03

1.E+04

mmended R

ISO

()

10k

1.E+02

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06

Rec

Normalized Load Capacitance;

MIN

(F)

100

100p 1n 10n 100n 1μ

MIN

= 1 to 10

MIN

= 100

OUT

REF

MCP6N11

Where:

α≤0.25

≥ G

MIN

GBWP

= Gain Bandwidth Product

= C

+ C

+ (PCB stray capacitance)

For G

=1:

GBWP

------------------------------

For G

>1: