Datasheet

© 2011 Microchip Technology Inc. DS25073A-page 31
MCP6N11
4.2.2 ENABLE/V
OS
CALIBRATION
(EN/CAL
)
These parts have a Normal mode, a Low Power mode
and a V
OS
Calibration mode.
When the EN/CAL
pin is high and the internal POR
(with delay) indicates that power is good, the part
operates in its Normal mode.
When the EN/CAL
pin is low, the part operates in its
Low Power mode. The quiescent current (at V
SS
) drops
to -2.5 µA (typical), the amplifier output is put into a
high-impedance state. Signals at the input pins can
feed through to the output pin.
When the EN/CAL
pin goes high and the internal POR
(with delay) indicates that power is good, the amplifier
internally corrects its input offset voltage (V
OS
) with the
internal common mode voltage at mid-supply (V
DD
/2)
and the output tri-stated (after t
OFF
). Once V
OS
Calibra-
tion is completed, the amplifier is enabled and normal
operation resumes.
The EN/CAL
pin does not operate normally when left
floating. Either drive it with a logic output, or tie it high
so that the part is always on.
4.2.3 POR WITH DELAY
The internal POR makes sure that the input offset
voltage (V
OS
) is calibrated whenever the supply
voltage goes from low voltage (< V
PRL
) to high voltage
(> V
PRH
). This prevents corruption of the V
OS
trim reg-
isters after a low-power event.
After the POR goes high, the internal circuitry adds a
fixed delay (t
PLH
), before telling the V
OS
Calibration
circuitry (see Figure 4-2) to start. If the EN/CAL
pin is
toggled during this time, the fixed delay is restarted
(takes an additional time t
PLH
).
4.2.4 PARITY DETECTOR
A parity error detector monitors the memory contents
for any corruption. In the rare event that a parity error is
detected (e.g., corruption from an alpha particle), a
POR event is automatically triggered. This will cause
the input offset voltage to be re-corrected, and the op
amp will not return to normal operation for a period of
time (the POR turn on time, t
PLH
).
4.2.5 RAIL-TO-RAIL OUTPUT
The Minimum Output Voltage (V
OL
) and Maximum
Output Voltage (V
OH
) specs describe the widest output
swing that can be achieved under the specified load
conditions.
The output can also be limited when V
IP
or V
IM
exceeds
V
IVL
or V
IVH
, or when V
DM
exceeds V
DML
or V
DMH
.
4.3 Applications Tips
4.3.1 MINIMUM STABLE GAIN
There are different options for different Minimum Stable
Gains (1, 2, 5, 10 and 100 V/V; see Tab l e 1 -1). The
differential gain (G
DM
) needs to be greater than or
equal to G
MIN
in order to maintain stability.
Picking a part with higher G
MIN
has the advantages of
lower Input Noise Voltage Density (e
ni
), lower Input
Offset Voltage (V
OS
) and increased Gain Bandwidth
Product (GBWP); see Table 1. The Differential Input
Voltage Range (V
DMR
) is lower for higher G
MIN
, but the
output voltage range would limit V
DMR
anyway, when
G
DM
≥ 2.
4.3.2 CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for amplifiers. As the load capacitance
increases, the feedback loop’s phase margin
decreases, and the closed-loop bandwidth is reduced.
This produces gain peaking in the frequency response,
with overshoot and ringing in the step response. Lower
gains (G
DM
) exhibit greater sensitivity to capacitive
loads.
When driving large capacitive loads with these
instrumentation amps (e.g., > 100 pF), a small series
resistor at the output (R
ISO
in Figure 4-8) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-8: Output Resistor, R
ISO
stabilizes large capacitive loads.
Figure 4-9 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
G
MIN
/G
DM
), where
G
DM
is the circuit’s differential gain (1 + R
F
/R
G
) and
G
MIN
is the minimum stable gain.
R
ISO
V
OUT
C
L
V
1
V
DD
V
2
V
REF
V
FG
R
F
R
G
U
1
MCP6N11