Datasheet

© 2011 Microchip Technology Inc. DS25073A-page 29
MCP6N11
4.1.4 AC PERFORMANCE
The bandwidth of these amplifiers depends on G
DM
and G
MIN
:
EQUATION 4-10:
The bandwidth at the maximum output swing is called
the Full Power Bandwidth (f
FPBW
). It is limited by the
Slew Rate (SR) for many amplifiers, but is close to f
BW
for these parts:
EQUATION 4-11:
CMRR is constant from DC to about 1 kHz.
4.1.5 NOISE PERFORMANCE
As shown in Figures 2-41 and 2-42, the 1/f noise
causes an apparent wander in the DC output voltage.
Changing the measurement time or bandwidth has little
effect on this noise.
We recommend re-calibrating V
OS
periodically, to
reduce 1/f noise wander. For example, V
OS
could be
re-calibrated at least once every 15 minutes; more
often when temperature or V
DD
change significantly.
4.2 Functional Blocks
4.2.1 RAIL-TO-RAIL INPUTS
Each input stage uses one PMOS differential pair at the
input. The output of each differential pair is processed
using current mode circuitry. The inputs show no
crossover distortion vs. common mode voltage.
With this topology, the inputs (V
IP
and V
IM
) operate
normally down to V
SS
– 0.2V and up to V
DD
+ 0.15V at
room temperature (see Figure 2-11). The input offset
voltage (V
OS
) is measured at V
CM
=V
SS
–0.2V and
V
DD
+ 0.15V (at +25°C), to ensure proper operation.
4.2.1.1 Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figures 2-18 and 2-50 show an input voltage
exceeding both supplies with no phase inversion.
The input devices also do not exhibit phase inversion
when the differential input voltage exceeds its limits;
see Figures 2-22 and 2-51.
4.2.1.2 Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”). This requirement is independent of the
current limits discussed later on.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (I
B
).
FIGURE 4-4: Simplified Analog Input ESD
Structures.
Where:
f
BW
= -3 dB bandwidth
f
GBWP
= Gain bandwidth product
f
BW
f
GBWP
G
DM
---------------≈
0.50 MHz()G
MIN
G
DM
⁄ (), ≈
0.35 MHz()G
MIN
G
DM
⁄ (), ≈
G
MIN
=1, …,10
G
MIN
=100
Where:
V
O
= Maximum output voltage swing
≈ V
OH
–V
OL
f
FPBW
SR
π V
O
---------- ≈
f
BW
≈
, for these parts
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IP
V
SS
Input
Stage
Bond
Pad
V
IM
of
INA Input