Datasheet
© 2011 Microchip Technology Inc. DS25073A-page 27
MCP6N11
4.0 APPLICATIONS
The MCP6N11 instrumentation amplifier (INA) is
manufactured using Microchip’s state of the art CMOS
process. It is low cost, low power and high speed,
making it ideal for battery-powered applications.
4.1 Basic Performance
4.1.1 STANDARD CIRCUIT
Figure 4-1 shows the standard circuit configuration for
these INAs. When the inputs and output are in their
specified ranges, the output voltage is approximately:
EQUATION 4-1:
FIGURE 4-1: Standard Circuit.
For normal operation, keep:
•V
IP
, V
IM
, V
REF
and V
FG
between V
IVL
and V
IVH
•V
IP
– V
IM
(i.e., V
DM
) between V
DML
and V
DMH
•V
OUT
between V
OL
and V
OH
4.1.2 ARCHITECTURE
Figure 4-2 shows the block diagram for these INAs.
FIGURE 4-2: MCP6N11 Block Diagram.
The input offset voltage (V
OS
) is corrected by the
voltage V
TR
. Each time a V
OS
Calibration event occurs,
V
TR
is updated to the best value (at that moment).
These events are triggered by either powering up
(monitored by the POR) or by toggling the EN/CAL
pin
high. The current out of G
M3
(I
3
) is constant and very
small (assumed to be zero in the following discussion).
The input signal is applied to G
M1
. Equation 4-2 shows
the relationships between the input voltages (V
IP
and
V
IM
) and the common mode and differential voltages
(V
CM
and V
DM
).
EQUATION 4-2:
The negative feedback loop includes G
M2
, R
M4
, R
F
and
R
G
. These blocks set the DC open-loop gain (A
OL
) and
the nominal differential gain (G
DM
):
EQUATION 4-3:
A
OL
is very high, so I
4
is very small and I
1
+ I
2
≈ 0. This
makes the differential inputs to G
M1
and G
M2
equal in
magnitude and opposite in polarity. Ideally, this gives:
EQUATION 4-4:
For an ideal part, changing V
CM
, V
SS
or V
DD
produces
no change in V
OUT
. V
REF
shifts V
OUT
as needed.
The different G
MIN
options change G
M1
, G
M2
and the
internal compensation capacitor. This results in the
performance trade-offs shown in Tab le 1.
V
OUT
≈ V
REF
+G
DM
V
DM
Where:
G
DM
=1+R
F
/R
G
V
OUT
V
IP
V
DD
V
IM
V
REF
V
FG
R
F
R
G
U
1
MCP6N11
R
F
V
FG
V
OUT
Low Power
V
SS
V
DD
EN/CAL
V
OUT
V
OS
Calibration
V
REF
R
M4
G
M2
Σ
I
2
V
REF
I
4
G
M3
I
3
V
TR
R
G
V
IP
V
IM
G
M1
I
1
V
IP
V
IM
POR
V
IP
V
CM
V
DM
2
⁄
+=
V
IM
V
CM
V
DM
2
⁄
–=
V
CM
V
IP
V
IM
+()2
⁄
=
V
DM
V
IP
V
IM
–=
A
OL
G
M2
R
M4
=
G
DM
1R
F
R
G
⁄
+=
V
FG
V
REF
–()V
DM
=
V
OUT
V
DM
G
DM
V
REF
+=