MCP6N11 500 kHz, 800 µA Instrumentation Amplifier Features Description • Rail-to-Rail Input and Output • Gain Set by 2 External Resistors • Minimum Gain (GMIN) Options: 1, 2, 5, 10 or 100 V/V • Common Mode Rejection Ratio (CMRR): 115 dB (typical, GMIN = 100) • Power Supply Rejection Ratio (PSRR): 112 dB (typical, GMIN = 100) • Bandwidth: 500 kHz (typical, Gain = GMIN) • Supply Current: 800 μA/channel (typical) • Single Channel • Enable/VOS Calibration pin: (EN/CAL) • Power Supply: 1.8V to 5.
MCP6N11 Minimum Gain Options Table 1 shows key specifications that differentiate between the different minimum gain (GMIN) options. See Section 1.0 “Electrical Characteristics”, Section 6.0 “Packaging Information” and Product Identification System for further information on GMIN. TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS Part No. GMIN VOS ∆VOS/∆TA CMRR (dB) PSRR (dB) (V/V) (±mV) (±µV/°C) Min. Nom. Max. Typ. VDD = 5.5V Min. MCP6N11-001 1 MCP6N11-002 MCP6N11-005 eni Eni (µVP-P) (nV/√Hz) Nom. Nom.
MCP6N11 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † VDD – VSS .......................................................................6.5V Current at Input Pins †† ...............................................±2 mA Analog Inputs (VIP and VIM) †† ..... VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage....................................... |VDD – VSS| Output Short Circuit Current ................................
MCP6N11 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and GDM = GMIN; see Figure 1-6 and Figure 1-7.
MCP6N11 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and GDM = GMIN; see Figure 1-6 and Figure 1-7. Parameters Sym Min Typ Max Units GMIN Conditions all Input Differential Mode Voltage (VDM) (Note 4) Differential Input Voltage Range VDML -2.7/GMIN — — V VDMH — — +2.
MCP6N11 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Parameters Sym Min Typ — 0.50 GMIN — 35 Max Units GMIN — MHz 1 to 10 — MHz 100 Conditions AC Response Gain Bandwidth Product GBWP Phase Margin PM — 70 — ° all Open-Loop Output Impedance ROL — 0.
MCP6N11 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Parameters Sym Min Typ Max Units GMIN Conditions EN/CAL Low Specifications EN/CAL Logic Threshold, Low VIL VSS — 0.2 VDD V EN/CAL Input Current, Low IENL — -0.1 — nA EN/CAL = 0V -7 -2.
MCP6N11 1.3 Timing Diagrams tENLH VDM ±(1V)/GDM EN/CAL tENOL tOFF VCM VOUT tIRC FIGURE 1-5: High-Z tON EN/CAL Timing Diagram. VOUT FIGURE 1-1: Common Mode Input Overdrive Recovery Timing Diagram. VCM VDD/2 VDM tIRD VOUT FIGURE 1-2: Differential Mode Input Overdrive Recovery Timing Diagram. VCM VDD/2 VDM tOR VOUT FIGURE 1-3: Timing Diagram. Output Overdrive Recovery 1.8V VPRL – 0.1V VDD tPHL VOUT FIGURE 1-4: DS25073A-page 8 High-Z VPRH + 0.1V 0V tPLH POR Timing Diagram.
MCP6N11 1.4 1.4.1 DC Test Circuits 1.4.2 INPUT OFFSET TEST CIRCUIT Figure 1-6 is used for testing the INA’s input offset errors and input voltage range (VE, VIVL and VIVH; see Section 1.5.1 “Input Offset Related Errors” and Section 1.5.2 “Input Offset Common Mode Nonlinearity”). U2 is part of a control loop that forces VOUT to equal VCNT; U1 can be set to any bias point. VDD VCM 2.
MCP6N11 1.5 Explanation of DC Error Specs 1.5.1 Based on the measured VE data, we obtain the following linear fit: INPUT OFFSET RELATED ERRORS The input offset error (VE) is extracted from input offset measurements (see Section 1.4.
MCP6N11 Figure 1-9 shows VED vs. VDM, as well as a linear fit line (VED_LIN) based on VE and gE. The op amp is in standard conditions (ΔVOUT = 0, etc.). VDM is swept from VDML to VDMH. VED, VED_LIN (V) VED_LIN V3 VED V2 V1 ΔVED VDML VDM (V) 0 VDMH FIGURE 1-9: Differential Input Error vs. Differential Input Voltage.
MCP6N11 NOTES: DS25073A-page 12 © 2011 Microchip Technology Inc.
MCP6N11 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
MCP6N11 2.5 Normalized d Input Offset Voltage; GMINVOS (mV) 2.0 1.5 1.0 0.5 0.0 -0.5 -40°C +25°C +85°C +125°C -1.0 -1.5 Representative Part VCM = VSS GMIN = 1 to 10 RTO -2.0 10 Representative Part VCM = VDD GMIN = 100 RTO 8 6 4 2 0 -2 -4 -40°C +25°C +85°C +125°C -6 -8 Power Supply Voltage 25 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.0 Normalized d Input Offset Voltage; GMINVOS (mV) Norm malized d Inputt Offse et Volta age; GMINVOS (mV) 2.
MCP6N11 0.4 VIVH – VDD 1 Wafer Lot 0.3 0.2 0.1 VDD = 1.8V VDD = 5.5V 00 0.0 -0.1 02 -0.2 -0.3 -0.4 VIVL – VSS -0.5 1.0 0.5 0.0 -0.5 +125°C +85 +85°C +25°C -40°C -1.0 -1.5 2.0 1.0 0.5 0.0 -0.5 +125°C +85°C +25°C -40°C -1.0 -1.5 15 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VDD = 5.5V Representative Part GMIN = 100 RTO 10 5 0 -5 +125°C +85°C +25°C -40°C -10 5 0 -5 +125°C +85°C +25°C -40°C 2.5 FIGURE 2-13: Normalized Input Offset Voltage vs.
MCP6N11 5 110 105 Normalized Differential Input Errror; GMINVED (mV) Norm malized d DC O Open-Lo oop Ga ain; AOL / GM MIN (dB)) Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. VDD = 5.5V VDD = 1.8V 100 95 90 85 80 75 GMIN = 1 to 10 GMIN = 100 70 65 3 2 0 -1 VDD = 5.
MCP6N11 Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 2.5 1.E-08 10n Input Bias s, Offset Currents (nA) Input Bias s, Offset Currents (A) VDD = 5.5V VCM = VDD 1.E-09 1n IB 1.E-10 100p 1.E-11 10p | IOS | IOS 10 -1.0 -1.5 -2.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.
MCP6N11 Power Supply Voltage (V) 1100 1000 900 800 700 600 500 400 6.0 5.5 5.0 Common Mode Input Voltage (V) FIGURE 2-31: Supply Current vs. Common Mode Input Voltage. 6.5 6.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 300 200 100 0 5.5 +125°C +85°C +25°C 40 -40°C 0.0 Supply Current (μA) FIGURE 2-29: Output Short Circuit Current vs. Power Supply Voltage. 4.5 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -50 4.0 -40 3.5 -30 3.0 -20 2.5 -10 VDD = 1.8V 2.
MCP6N11 Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 100 VDD = 5.5V Normaliized Ga N ain Ban ndwith h Productt; GBW WP/GMINN (MHz)) 90 80 60 50 40 GMIN = 1 GMIN = 2 GMIN = 5 GMIN = 10 GMIN = 100 30 20 10 0 1k 1.E+03 10k 100k 1.E+04 1.E+05 Frequency (Hz) FIGURE 2-32: 0.
MCP6N11 Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 2.3 Noise 0.5 RTO 100 100μ GMIN = 100 10 10μ 10 GMIN = 10 GMIN = 5 GMIN = 2 GMIN = 1 1 1μ 0.3 02 0.2 0.1 00 0.0 -0.1 -0.2 -0.3 -0.5 0 2.0 12 15 1.5 GMIN = 100 GMIN = 10 GMIN = 5 GMIN = 2 GMIN = 1 8 6 Norma alized Input N Noise; GMINeni(tt) (mV)) 14 10 VDD = 1.8V VDD = 5.
MCP6N11 Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Time Response GMIN = 1 to 10 GMIN = 100 0 2 4 FIGURE 2-43: Response. 6 8 10 12 Time (μs) 16 18 4.5 4.0 3.5 3.0 GMIN = 1 to 10 GMIN = 100 2.5 VDD = 1.8V 1 GMIN = 1 to 10 GMIN = 100 0 10k 1.E+4 2.0 1.5 1.0 0.5 1000 VDD = 5.5V 100 VDD = 1.
MCP6N11 Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. 4 GDM = 2GMIN VREF = 0.75VDD VDD = 5.5V 100 GMIN = 1 VDD = 1.8V GMIN = 10 10 GMIN = 100 1 In nput, O Output Voltag ges (V) Output Overdrive Recovery; tOR (μs) 1000 VDD = 5.
MCP6N11 Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. Enable/Calibration and POR Responses 30 VDD = 1.8V VL = 0V 1.8 1.6 1.4 Calibration Starts 1.2 1.0 INA turns off INA turns on 0.8 0.6 0.4 EN/CAL 0.2 VOUT 0.0 VDD = 5.5V 20 VDD = 1.8V 15 10 5 0 -0.2 0 10 20 30 40 50 60 Time (ms) 70 80 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.
MCP6N11 Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7. EN/CAL = 0V 1.E-07 100n Ou utput L Leakag ge Currrent (A A) Negative P Power S Supply y Curre ent; ISS (μ μA) 0.0 EN/CAL = 0V VDD = 5.5V 1.E-08 10n -0.5 1.E-09 1n -1.0 +125°C +85°C 1.E-10 100p -1.5 +125°C +85°C +85 C +25°C -40°C -2.0 -2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
MCP6N11 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6N11 SOIC TDFN Symbol Description 1 1 VFG Feedback Input 2 2 VIM Inverting Input 3 3 VIP Non-inverting Input 4 4 VSS Negative Power Supply 5 5 VREF Reference Input 6 6 VOUT Output 7 7 VDD Positive Power Supply 8 8 EN/CAL — 9 EP 3.
MCP6N11 NOTES: DS25073A-page 26 © 2011 Microchip Technology Inc.
MCP6N11 4.0 APPLICATIONS The MCP6N11 instrumentation amplifier (INA) is manufactured using Microchip’s state of the art CMOS process. It is low cost, low power and high speed, making it ideal for battery-powered applications. 4.1 Basic Performance 4.1.1 STANDARD CIRCUIT Figure 4-1 shows the standard circuit configuration for these INAs. When the inputs and output are in their specified ranges, the output voltage is approximately: The input offset voltage (VOS) is corrected by the voltage VTR.
MCP6N11 4.1.3 DC ERRORS EQUATION 4-6: Section 1.5 “Explanation of DC Error Specs” defines some of the DC error specifications.
MCP6N11 4.1.4 AC PERFORMANCE The bandwidth of these amplifiers depends on GDM and GMIN: EQUATION 4-10: f GBWP f BW ≈ --------------G DM ≈ ( 0.50 MHz ) ( G MIN ⁄ G DM ), ≈ ( 0.35 MHz ) ( G MIN ⁄ G DM ), Where: GMIN = 1, …, 10 GMIN = 100 fBW = -3 dB bandwidth fGBWP = Gain bandwidth product The bandwidth at the maximum output swing is called the Full Power Bandwidth (fFPBW).
MCP6N11 VDD U1 D1 MCP6N11 V1 D2 V2 FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. 4.2.1.3 Input Current Limits In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see Section 1.1 “Absolute Maximum Ratings †”). This requirement is independent of the voltage limits previously discussed. 4.2.1.4 Input Voltage Ranges Figure 4-7 shows possible input voltage values (VSS = 0V).
MCP6N11 4.2.2 ENABLE/VOS CALIBRATION (EN/CAL) These parts have a Normal mode, a Low Power mode and a VOS Calibration mode. When the EN/CAL pin is high and the internal POR (with delay) indicates that power is good, the part operates in its Normal mode. When the EN/CAL pin is low, the part operates in its Low Power mode. The quiescent current (at VSS) drops to -2.5 µA (typical), the amplifier output is put into a high-impedance state. Signals at the input pins can feed through to the output pin.
MCP6N11 In this data sheet, RF + RG = 10 kΩ for most gains (0Ω for GDM = 1); see Table 1-6. This choice gives good Phase Margin. In general, RF (Figure 4-10) needs to meet the following limits to maintain stability: Reco ommended RISO ( ) 1.E+04 10k EQUATION 4-12: 1.E+03 1k For GDM = 1: RF = 0 GMIN = 1 to 10 GMIN = 100 1.E+02 100 100p 1.E-10 1n 10n 100n 1.E-09 1.E-08 1.E-07 Normalized Load Capacitance; CL GMIN/GDM (F) 1μ 1.E-06 2 FIGURE 4-9: Recommended RISO Values for Capacitive Loads.
MCP6N11 4.4 4.4.1 Typical Applications 4.4.3 HIGH INPUT IMPEDANCE DIFFERENCE AMPLIFIER Figure 4-11 shows the MCP6N11 used as a difference amplifier. The inputs are high impedance and give good CMRR performance. VDD U1 Figure 4-13 shows the MCP6N11 INA used as to detect and amplify the high side current in a battery powered design. The INA gain is set at 21 V/V, so VOUT changes 210 mV for every 1 mA of IDD current. The best GMIN option to pick would be a gain of 10 (MCP6N11-010).
MCP6N11 NOTES: DS25073A-page 34 © 2011 Microchip Technology Inc.
MCP6N11 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP6N11 instrumentation amplifiers. 5.1 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs.
MCP6N11 NOTES: DS25073A-page 36 © 2011 Microchip Technology Inc.
MCP6N11 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead SOIC (150 mil) (MCP6N11) Example 6N11001E e3 1121 SN^^ 256 NNN Note: 8-Lead TDFN (2×3) (MCP6N11) Example Device Legend: XX...X Y YY WW NNN e3 * Note: Code MCP6N11-001 AAQ MCP6N11-002 AAR MCP6N11-005 AAS MCP6N11-010 AAT MCP6N11-100 AAU Note: The example is for a MCP6N11-001 part.
MCP6N11 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25073A-page 38 © 2011 Microchip Technology Inc.
MCP6N11 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
MCP6N11 & ! " #$% ! " # $ % & "' " " ( $ ) % *++&&& ! !+ $ DS25073A-page 40 © 2011 Microchip Technology Inc.
MCP6N11 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
MCP6N11 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25073A-page 42 © 2011 Microchip Technology Inc.
MCP6N11 & ' ( ) * + ,- - ./ ! "0'( % ! " # $ % & "' " " ( $ ) % *++&&& ! !+ $ © 2011 Microchip Technology Inc.
MCP6N11 NOTES: DS25073A-page 44 © 2011 Microchip Technology Inc.
MCP6N11 APPENDIX A: REVISION HISTORY Revision A (October 2011) • Original Release of this Document. © 2011 Microchip Technology Inc.
MCP6N11 NOTES: DS25073A-page 46 © 2011 Microchip Technology Inc.
MCP6N11 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP6N11 NOTES: DS25073A-page 48 © 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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