Datasheet

MCP6L71/1R/2/4
DS22145A-page 14 © 2009 Microchip Technology Inc.
4.4 Supply Bypass
With this family of operational amplifiers, the power
supply pin (V
DD
for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.5 Unused Amplifiers
An unused op amp in a quad package (MCP6L74)
should be configured as shown in Figure 4-3. These
circuits prevent the output from toggling and causing
crosstalk. In Circuit A, R
1
and R
2
produce a voltage
within its output voltage range (V
OH
, V
OL
). The op amp
buffers this voltage, which can be used elsewhere in
the circuit. Circuit B uses the minimum number of
components and operates as a comparator.
FIGURE 4-3: Unused Op Amps.
4.6 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
12
Ω. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6L71/1R/2/4 family’s bias current at +25°C (1 pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-4 shows an example of this type of layout.
FIGURE 4-4: Example Guard Ring
Layout.
1. For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
a) Connect the guard ring to the non-inverting
input pin (V
IN
+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., V
DD
/2 or ground).
b) Connect the inverting pin (V
IN
–) to the input
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity Gain Buffer:
a) Connect the guard ring to the inverting input
pin (V
IN
–). This biases the guard ring to the
common mode input voltage.
b) Connect the non-inverting pin (V
IN
+) to the
input with a wire that does not touch the
PCB surface.
4.7 Application Circuits
4.7.1 INVERTING INTEGRATOR
An inverting integrator is shown in Figure 4-5. The
circuit provides an output voltage that is proportional to
the negative time-integral of the input. The additional
resistor R
2
limits DC gain and controls output clipping.
To minimize the integrator’s error for slow signals, the
value of R
2
should be much larger than the value of R
1
.
FIGURE 4-5: Inverting Integrator.
¼MCP6L74(A)
V
DD
¼ MCP6L74 (B)
R
1
R
2
V
DD
V
DD
V
REF
V
REF
V
DD
R
2
R
1
R
2
+
------------------
⋅=
Guard Ring
V
IN
–V
IN
+
+
_
C
1
R
2
V
IN
V
OUT
MCP6L71
R
2
R
1
»
V
OUT
1
R
1
C
1
------------ -
V
IN
td
0
t
∫
–=
R
1