Datasheet

MCP6G01/1R/1U/2/3/4
DS22004B-page 22 © 2006 Microchip Technology Inc.
FIGURE 4-6: Recommended R
ISO
.
4.6 Layout Considerations
Good PC board layout techniques will help achieve the
performance shown in Section 1.0 “Electrical
Characteristics” and Section 2.0 “Typical
Performance Curves”. It will also help minimize
Electromagnetic Compatibility (EMC) issues.
Because the MCP6G01/1R/1U/2/3/4 SGAs’ frequency
response reaches unity gain at 10 MHz when G = 50, it
is important to use good PCB layout techniques. Any
parasitic coupling at high frequency might cause
undesired peaking. Filtering high frequency signals
(i.e., fast edge rates) can help.
4.6.1 COMPONENT PLACEMENT
Separate different circuit functions: digital from analog,
low speed from high speed, and low power from high
power. This will reduce crosstalk.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
4.6.2 SUPPLY BYPASS
Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the V
DD
pin for good, high frequency
performance. It must connect directly to ground.
Use a bulk bypass capacitor (i.e., 1.0 µF to 10 µF)
within 100 mm of the V
DD
pin. It needs to connect to
ground, and provides large, slow currents. This
capacitor may be shared with other nearby analog
parts.
Ground plane is important, and power plane(s) can
also be of great help. High frequency (e.g., multi-layer
ceramic capacitors), surface mount components
improve the supply’s performance.
4.6.3 INPUT SOURCE IMPEDANCE
The sources driving the inputs of the SGAs need to
have reasonably low source impedance at higher
frequencies. Figure 4-7 shows how the external source
resistance (R
S
), SGA package pin capacitance (C
P1
),
and SGA package pin-to-pin capacitance (C
P2
) form a
positive feedback voltage divider network. Feedback
may cause frequency response peaking and step
response overshoot and ringing.
FIGURE 4-7: Positive Feedback Path.
Figure 2-10 shows the crosstalk (referred to input) that
results when a hostile signal is connected to the other
inputs (e.g., V
INB
through V
IND
), and the input of
interest (e.g., V
INA
) has R
S
connected to GND. A gain
of +50 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing R
S
increases the crosstalk as expected. At a source
impedance of 10 MΩ, there is noticeable change in
behavior.
Most designs should use a source resistance (R
S
) no
larger than 10 MΩ. Careful attention to layout parasitics
and proper component selection will help minimize this
effect. When a source impedance larger than 10 MΩ
must be used, place a capacitor in parallel to C
P1
to
reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk)
peaking, yet small enough to allow a reasonable signal
bandwidth.
4.6.4 SIGNAL COUPLING
The input pins of the MCP6G01/1R/1U/2/3/4 family of
SGAs are high impedance. This makes them especially
susceptible to capacitively coupled noise. Using a
ground plane helps reduce this problem.
When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.
10
100
1,000
10 100 1,000 10,000 100,000
Load Capacitance (F)
Recommended R
ISO
(
:
)
10p 100p 1n 100n
For all gains
10n
V
S
MCP6G0X
V
OUT
R
S
C
P1
C
P2