Datasheet

© 2006 Microchip Technology Inc. DS22004B-page 21
MCP6G01/1R/1U/2/3/4
R
LAD
is intended to be driven at the V
SS
pin by a low
impedance voltage source. The power supply driving
the V
SS
pin should have an output impedance less than
0.1Ω to maintain reasonable gain accuracy.
4.3 MCP6G03 Chip Select (CS)
The MCP6G03 is a single amplifier with chip select
(CS). When CS is high, the internal op amp is shut
down and its output placed in a high-Z state. The
resistive ladder is always connected between V
SS
and
V
OUT
; even in shutdown. This means that the output
resistance will be 350 kΩ (typ.), with a path for output
signals to appear at the input. The supply current at
V
SS
includes the current through the load resistor and
ladder resistors; it also includes current from the CS
pin
to V
SS
. When CS is low, the amplifier is enabled. If CS
is left floating, the amplifier may not operate properly.
Figure 1-2 and Figure 2-43 show how the output
voltage and supply current response to a CS
pulse.
4.4 Gain Select (GSEL)
The amplifier can be set to the gains +1 V/V, +10 V/V,
and +50 V/V using one input pin (GSEL). At the same
time, different compensation capacitors are selected to
optimize the bandwidth vs. slew rate trade-off (see
Tab l e 4- 1 ). Tab le 4-2 shows how to change the gain
using a GPIO pin on a microcontroller and Tab le 4-3
shows how to hard wire the gain (i.e., using PCB
wiring).
TABLE 4-2: MCU DRIVEN GAIN
SELECTION
TABLE 4-3: HARD WIRED GAIN
SELECTION
4.5 Capacitive Load and Stability
Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6G01/1R/1U/2/3/4
family of SGAs (Figure 2-30 and Figure 2-34). As the
load capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier’s phase margin and bandwidth.
When driving large capacitive loads with these SGAs
(i.e., > 60 pF), a small series resistor at the output
(R
ISO
in Figure 4-5) improves the internal amplifier’s
stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
FIGURE 4-5: SGA Circuit for Large
Capacitive Loads.
Figure 4-6 gives recommended R
ISO
values for
different capacitive loads. After selecting R
ISO
for your
circuit, double check the resulting frequency response
peaking and step response overshoot on the bench.
Modify R
ISO
’s value until the response is reasonable at
all gains.
Gain MCU Pin’s State
+1 V/V Output PIC’s V
REF
at V
DD
/2
Digital Output High-Z (Notes 1)
Output V
DD
/2 PWM signal (Notes 2)
+10 V/V Digital Output driven Low
+50 V/V Digital Output driven High
Note 1: See Section 4.8.1 “Driving the Gain
Select Pin with a Microcontroller GPIO
Pin”.
2: See Section 4.8.2 “Driving the Gain
Select Pin with a PWM Signal”
Selected Gain Possible GSEL Drivers
+1 V/V Open Circuit (Note 1)
Low impedance source at V
DD
/2
+10 V/V Tied to GND (0V)
+50 V/V Tied to V
DD
Note 1: The GSEL pin floats to mid-supply
(V
DD
/2); a bypass capacitor may be
needed.
V
IN
V
OUT
MCP6G0X
R
ISO
C
L