Datasheet

MCP6G01/1R/1U/2/3/4
DS22004B-page 20 © 2006 Microchip Technology Inc.
4.1.4 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltages that go too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-2: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the V
IN
pins (see Section
“Absolute Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V
IN
) from going too far below ground, and the resistor
R
1
limits the possible current drawn out of the input pin.
Diode D
1
prevents the input pin (V
IN
) from going too far
above V
DD
. When implemented as shown, resistor R
1
also limits the current through D
1
.
FIGURE 4-3: Protecting the Analog
Inputs.
It is also possible to connect the diode to the left of the
resistor R
1
. In this case, the current through the diode
D
1
needs to be limited by some other mechanism. The
resistor then serves as in-rush current limiter; the DC
current into the input pin (V
IN
) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (V
CM
) is below
ground (V
SS
); see Figure 2-17. Applications that are
high impedance may need to limit the useable voltage
range.
4.1.5 RAIL-TO-RAIL OUTPUT
The maximum output voltage swing is the maximum
swing possible under a particular amplifier load current.
The amplifier load current is the sum of the external
load current (I
OUT
) and the current through the ladder
resistance (I
LAD
); see Figure 4-4.
EQUATION 4-2:
FIGURE 4-4: Amplifier Load Current.
See Figure 2-20 for the typical output headroom
(V
DD
– V
OH
or V
OL
– V
SS
) as a function of amplifier
load current.The specification table states the output
can reach within 10 mV of either supply rail when
R
L
= 100 kΩ.
4.2 Resistor Ladder
The resistor ladder shown in Figure 4-1
(R
LAD
=R
F
+R
G
) sets the gain. Placing the gain
switches in series with the inverting input reduces the
parasitic capacitance, distortion, and gain mismatch.
R
LAD
is an additional load on the output of the SGA and
causes additional current draw from the supplies.
When CS
is high, the SGA is shut down (low power).
R
LAD
is still attached to the V
OUT
and V
SS
pins. Thus,
these pins and the internal amplifier’s inverting input
are all connected through R
LAD
and the output is not
high-Z (unlike the internal op amp).
R
LAD
contributes to the output noise; see Figure 2-9.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
V
SS
to the rest of
Input
Stage
the amplifier
V
1
MCP6G0X
R
1
V
DD
D
1
R
1
≥
V
SS
– (minimum expected V
1
)
2mA
V
OUT
V
IN
Where:
Amplifier Load Current I
OUT
I
LAD
+=
I
LAD
V
OUT
V
SS
–()
R
LAD
---------------------------------=
V
OUT
V
SS
R
LAD
I
OUT
I
LAD
MCP6G0X
V
IN