Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsLinear ICsLinear IC - Op-amp Multi-purpose SOIC 14 N

 2009-2012 Microchip Technology Inc. DS22194D-page 1

MCP660/1/2/3/4/5/9

Features

• Gain Bandwidth Product: 60 MHz (typical)

• Short Circuit Current: 90 mA (typical)

• Noise: 6.8 nV/Hz (typical, at 1 MHz)

• Rail-to-Rail Output

• Slew Rate: 32 V/µs (typical)

• Supply Current: 6.0 mA (typical)

• Power Supply: 2.5V to 5.5V

• Extended Temperature Range: -40°C to +125°C

Typical Applications

• Driving A/D Converters

• Power Amplifier Control Loops

• Barcode Scanners

• Optical Detector Amplifier

Design Aids

• SPICE Macro Models

•FilterLab

Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Description

The Microchip Technology, Inc. MCP660/1/2/3/4/5/9

family of operational amplifiers (op amps) features high

gain bandwidth product (60 MHz, typical) and high

output short circuit current (90 mA, typical). Some also

provide a Chip Select pin (CS

) that supports a Low

Power mode of operation. These amplifiers are

optimized for high speed, low noise and distortion,

single-supply operation with rail-to-rail output and an

input that includes the negative rail.

This family is offered in single (MCP661), single with

pin (MCP663), dual (MCP662) and dual with two

pins (MCP665), triple (MCP660), quad (MCP664)

and quad with two CS

pins (MCP669). All devices are

fully specified from -40°C to +125°C.

Typical Application Circuit

Power Driver with High Gain

OUT

MCP66X

60 MHz, 6 mA Op Amps

Summary of content (68 pages)

PAGE 1
MCP660/1/2/3/4/5/9 60 MHz, 6 mA Op Amps Features Description • • • • • • • • The Microchip Technology, Inc. MCP660/1/2/3/4/5/9 family of operational amplifiers (op amps) features high gain bandwidth product (60 MHz, typical) and high output short circuit current (90 mA, typical). Some also provide a Chip Select pin (CS) that supports a Low Power mode of operation.
PAGE 2
MCP660/1/2/3/4/5/9 Package Types MCP660 SOIC, TSSOP 11 VSS EP 17 VDD 3 VDD 4 VINA+ 5 10 VINB+ VINA- VOUTA 7 8 NC 6 VOUTB 5 MCP661 SOIC NC 1 8 NC 7 VDD VIN– 2 VIN+ 3 6 VOUT VIN+ 3 VSS 4 NC 1 5 NC VSS 4 EP 9 8 CS 7 VDD VSS 4 5 NC 6 VOUT MCP665 3x3 DFN* VOUTA VINAVINA+ VSS CSA 1 2 3 4 5 EP 11 MCP662 3x3 DFN* 8 CS VOUTA 1 8 VDD 7 VDD VINA- 2 VINA+ 3 7 VOUTB VINA- 2 6 VINB5 VINB+ VINA+ 3 6 VOUT 5 NC VSS 4 VOUTA 1 6 VDD VSS 5 CS 4 VIN- VIN+ 3 VOUTA 1 9 8 7 6 VIN
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MCP660/1/2/3/4/5/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. VDD – VSS ........................
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MCP660/1/2/3/4/5/9 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL and CS = VSS (refer to Figure 1-2). Parameters Sym Min Typ Max Units Conditions Maximum Output Voltage Swing VOL, VOH VSS + 25 — VDD  25 mV VDD = 2.5V, G = +2, 0.5V Input Overdrive VOL, VOH VSS + 50 — VDD  50 mV VDD = 5.5V, G = +2, 0.
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MCP660/1/2/3/4/5/9 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL, CL = 20 pF and CS = VSS (refer to Figure 1-1 and Figure 1-2). Parameters Sym Min Typ Max Units VIL VSS — 0.2VD V Conditions CS Low Specifications CS Logic Threshold, Low D CS Input Current, Low ICSL — -0.1 — nA CS Logic Threshold, High VIH 0.
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MCP660/1/2/3/4/5/9 1.3 Timing Diagram ICS 0 nA (typical) 1 µA (typical) 1 µA (typical) VIH VIL CS CF 6.8 pF tON VOUT ISS 1.4 High-Z On -6 mA (typical) -1 µA (typical) RF 10 k VP tOFF High-Z FIGURE 1-1: RG 10 k -1 µA (typical) Timing Diagram. Test Circuits The circuit used for most DC and AC tests is shown in Figure 1-2. This circuit can independently set VCM and VOUT; see Equation 1-1.
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MCP660/1/2/3/4/5/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 8
MCP660/1/2/3/4/5/9 Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 130 VDD = 2.5V Representative Part 1.5 1.0 DC Open-Loop Gain (dB) Input Offset Voltage (mV) 2.0 -40°C +25°C +85°C +125° C 0.5 0.0 -0.5 -1.0 -1.5 120 115 105 -50 1.0 0.5 +125° C +85°C +25°C 40°C 0.0 -0.5 -1.0 -1.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -2.
PAGE 9
MCP660/1/2/3/4/5/9 Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 1000 Input Bias, Offset Currents (pA) FIGURE 2-13: Input Bias Current vs. Input Voltage (below VSS). Input Bias, Offset Currents (pA) 60 IOS -200 6.0 5.5 5.0 4.5 -400 4.0 1p 1.E-12 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) 0 3.5 100p 1.E-10 10p 1.E-11 200 3.0 +125°C +85°C +25°C -40°C 2.5 10n 1.
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MCP660/1/2/3/4/5/9 Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. Other DC Voltages and Currents 9 8 Supply Current (mA/amplifier) VDD = 5.5V 100 VDD = 2.5V VOL – VSS 10 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 FIGURE 2-19: Supply Voltage. Supply Current vs. Power 6 Supply Current (mA/amplifier) VDD = 5.5V 20 15 10 VDD = 5.5V 5 VDD = 2.
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MCP660/1/2/3/4/5/9 Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 80 80 90 75 75 Gain Bandwidth Product (MHz) 100 80 70 60 50 CMRR PSRR+ PSRR- 30 20 65 65 VDD = 5.5V VDD = 2.5V 60 60 55 55 50 50 GBWP 45 45 FIGURE 2-21: Frequency. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 40 2.0 10M 1.E+7 1.5 1M 1.E+6 1.0 10k 100k 1.E+4 1.E+5 Frequency (Hz) 0.5 1k 1.E+3 0.0 100 1.E+2 -0.
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MCP660/1/2/3/4/5/9 10 150 9 8 140 7 6 5 GN = 1 V/V GN = 2 V/V GN  4 V/V 4 3 2 1 0 10p 1.0E-11 Channel-to-Channel Separation; RTI (dB) Gain Peaking (dB) Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 130 FIGURE 2-27: Gain Peaking vs. Normalized Capacitive Load. DS22194D-page 12 VCM = VDD/2 G = +1 V/V 120 110 100 90 80 70 60 100p 1n 1.0E-10 1.
PAGE 13
MCP660/1/2/3/4/5/9 Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. Noise and Distortion 1.E+4 10µ Input Noise; eni(t) (µV) 20 1.E+3 1µ 1.E+2 100n 10n 1.E+1 1 1.E+0 10 1.E+1 100 1.E+2 1k 1.E+3 10 5 0 -5 -10 Analog NPBW = 0.1 Hz Sample Rate = 2 SPS VOS = -953 µV -15 0 100k 10M 1M 1.E+7 1.E+5 1.E+6 10k 1.E+4 Frequency (Hz) FIGURE 2-29: vs. Frequency.
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MCP660/1/2/3/4/5/9 Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 2.5 Time Response VIN 0 Output Voltage (V) Output Voltage (10 mV/div) VDD = 5.5V G=1 VOUT 20 40 60 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 80 100 120 140 160 180 200 Time (ns) Non-inverting Small Signal VIN VOUT 100 200 FIGURE 2-38: Response.
PAGE 15
MCP660/1/2/3/4/5/9 Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. Maximum Output Voltage Swing (VP-P) 10 VDD = 5.5V VDD = 2.5V 1 0.1 100k 1.E+05 1M 10M 1.E+06 1.E+07 Frequency (Hz) 100M 1.E+08 FIGURE 2-41: Maximum Output Voltage Swing vs. Frequency.  2009-2012 Microchip Technology Inc.
PAGE 16
MCP660/1/2/3/4/5/9 Note: Unless indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. Chip Select Response 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.40 CS = VDD 0.35 CS Hysteresis (V) CS Current (µA) 2.6 0.30 0.20 0.10 0.05 0.00 FIGURE 2-42: Supply Voltage. -50 CS 2.0 1.5 VOUT 1.0 On 0.5 0.0 Off 100 125 CS Hysteresis vs. Ambient 4 3 VDD = 2.5V 2 1 VDD = 5.5V Off 0 -0.
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MCP660/1/2/3/4/5/9 CS = VDD 1.E-06 1µ Output Leakage Current (A) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 CS = VDD = 5.5V 100n 1.E-07 10n 1.E-08 1n 1.E-09 +125°C +85°C Power Supply Voltage (V) FIGURE 2-48: Quiescent Current in Shutdown vs. Power Supply Voltage.  2009-2012 Microchip Technology Inc. 6.5 6.0 5.5 5.0 4.5 4.0 3.5 100p 1.E-10 3.0 2.5 2.0 1.5 1.0 0.5 +125°C +85°C +25°C -40°C 0.
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MCP660/1/2/3/4/5/9 NOTES: DS22194D-page 18  2009-2012 Microchip Technology Inc.
PAGE 19
PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1.
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MCP660/1/2/3/4/5/9 3.1 Analog Outputs 3.4 Chip Select Digital Input (CS) The analog output pins (VOUT) are low-impedance voltage sources. The input (CS) is a CMOS, Schmitt-triggered input that places the part into a Low Power mode of operation. 3.2 3.5 Analog Inputs Exposed Thermal Pad (EP) The non-inverting and inverting inputs (VIN+, VIN-, …) are high-impedance CMOS inputs with low bias currents.
PAGE 21
MCP660/1/2/3/4/5/9 4.0 APPLICATIONS The MCP660/1/2/3/4/5/9 family is manufactured using the Microchip state-of-the-art CMOS process. It is designed for low-cost, low-power and high-speed applications. Its low supply voltage, low quiescent current and wide bandwidth make the MCP660/1/2/3/4/5/9 ideal for battery-powered applications. 4.1 When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD V1 Input 4.1.
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MCP660/1/2/3/4/5/9 4.2 Rail-to-Rail Output 4.2.1 Figure 4-5 shows the power calculations used for a single op amp: MAXIMUM OUTPUT VOLTAGE The Maximum Output Voltage (see Figure 2-16 and Figure 2-17) describes the output range for a given load. For example, the output voltage swings to within 50 mV of the negative rail with a 1 k load tied to VDD/2. 4.2.2 OUTPUT CURRENT Figure 4-4 shows the possible combinations of output voltage (VOUT) and output current (IOUT), when VDD = 5.5V.
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MCP660/1/2/3/4/5/9 The power derating across temperature for an op amp in a particular package can be easily calculated (assuming equal power dissipations): EQUATION 4-5: POAmax  TJmax – TA n JA Where: TJmax = absolute max. junction temperature Several techniques are available to reduce TJA for a given POAmax: • Lower JA - Use another package - PCB layout (ground plane, etc.) - Heat sinks and air flow • Reduce POAmax - Increase RL - Limit IOUT (using RSER) - Decrease VDD Improving Stability 4.4.
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MCP660/1/2/3/4/5/9 Figure 4-8 shows an op amp circuit that represents non-inverting amplifiers (VM is a DC voltage and VP is the input) or inverting amplifiers (VP is a DC voltage and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they include the op amp’s Common mode input capacitance (CCM), board parasitic capacitance and any capacitor placed in parallel. VP VM RN MCP66X CG 1.E+05 100k RF 1k 1.E+03 100 1.E+02 1 FIGURE 4-8: Capacitance.
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MCP660/1/2/3/4/5/9 4.5 MCP663 and MCP665 Chip Select 4.7 High Speed PCB Layout The MCP663 is a single amplifier with Chip Select (CS). When CS is pulled high, the supply current drops to 1 µA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 M (typical) pulldown resistor connected to VSS, so it will go low if the CS pin is left floating.
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MCP660/1/2/3/4/5/9 4.8 Typical Applications 4.8.1 4.8.3 50 LINE DRIVER Figure 4-10 shows the MCP661 driving a 50 line. The large output current (e.g., see Figure 2-18) makes it possible to drive a back-matched line (RM2, the 50 line and the 50 load at the far end) to more than ±2V (the load at the far end sees ±1V). It is worth mentioning that the 50 line and the 50 load at the far end together can be modeled as a simple 50 resistor to ground. -2.5V RG 301 FIGURE 4-10: RM2 49.
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MCP660/1/2/3/4/5/9 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP660/1/2/3/4/5/9 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP660/1/2/3/4/5/9 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the linear region of operation over the temperature range of the op amp. See the model file for information on its capabilities.
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MCP660/1/2/3/4/5/9 NOTES: DS22194D-page 28  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP661) Example XXNN YX25 6-Lead SOT-23 (MCP663) Example XXNN JE25 Example: 8-Lead TDFN (2 x 3) (MCP661) ABJ 210 25 8-Lead DFN (3x3)(MCP662) Example Device MCP662T-E/MF Code DABQ DABQ 1210 256 Note: Applies to 8-Lead 3x3 DFN Legend: XX...
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MCP660/1/2/3/4/5/9 Package Marking Information (Continued) Example: 8-Lead MSOP (3x3 mm) (MCP662) 662E 210256 Example: 8-Lead SOIC (150 mil) (MCP661, MCP662, MCP663) MCP661E 3 SN e^^1210 256 NNN 10-Lead DFN (3×3) (MCP665) Example Device MCP665 Code BAFD BAFD 1210 256 Note: Applies to 10-Lead 3x3 DFN Pin 1 Pin 1 10-Lead MSOP (MCP665) Example: 665EUN 210256 Legend: XX...
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MCP660/1/2/3/4/5/9 Package Marking Information (Continued) 14-Lead SOIC (.150”) (MCP660, MCP664) Example MCP660 3 E/SL e^^ 1210256 14-Lead TSSOP (MCP660, MCP664) Example XXXXXXXX YYWW NNN 664E/ST 1210 256 16-Lead QFN (4x4) (MCP669) PIN 1 Legend: XX...
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MCP660/1/2/3/4/5/9 .
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 6 Pitch e 0.95 BSC Outside Lead Pitch e1 1.90 BSC Overall Height A 0.90 Molded Package Thickness A2 0.89 1.45 1.
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MCP660/1/2/3/4/5/9 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 36  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 38  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 40  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 42  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 ! "# $%& ' * +, . # # $ # / ## +22--- 2 DS22194D-page 44 ! - / 0 # 1 / % # # ! #  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 46  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 . / # 0 1 4 ! 5 5&$7 ' * ./ . # # $ # / ## +22--- 2  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 48  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 50  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 UN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 UN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 52  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 10-Lead Plastic Micro Small Outline Package (UN) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 54  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 . # # $ # / ## +22--- 2 DS22194D-page 56 ! - / 0 # 1 / % # # ! #  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22194D-page 58  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 89 ; / # 0 1 4 ! <5<5&$% ' * ;/ .
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MCP660/1/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 NOTES: DS22194D-page 62  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 APPENDIX A: REVISION HISTORY Revision D (March 2012) The following is the list of modifications: Added the MSOP (8L) package for MCP662 and all related information throughout the document. Revision C (November 2011) The following is the list of modifications: 1. 2. 3. 4. 5. Added the SOT-23 (5L) and TDFN (8L) package option for MCP661 and SOT-23 (6L) package options for MCP663 and the related information throughout the document.
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MCP660/1/2/3/4/5/9 NOTES: DS22194D-page 64  2009-2012 Microchip Technology Inc.
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MCP660/1/2/3/4/5/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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MCP660/1/2/3/4/5/9 NOTES: DS22194D-page 66  2009-2012 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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