Datasheet

 2009-2013 Microchip Technology Inc. DS22143D-page 17
MCP6566/6R/6U/7/9
4.0 APPLICATIONS INFORMATION
The MCP6566/6R/6U/7/9 family of open-drain output
comparators are fabricated on Microchip’s
state-of-the-art CMOS process. They are suitable for a
wide range of high speed applications requiring low-
power consumption.
4.1 Comparator Inputs
4.1.1 NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel. This configuration
provides three regions of operation, one operates at
low input voltages, one at high input voltages, and one
at mid input voltage. With this topology, the input
voltage range is 0.3V above V
DD
and 0.3V below V
SS
,
while providing low offset voltage throughout the
common mode range. The input offset voltage is
measured at both V
SS
- 0.3V and V
DD
+ 0.3V to ensure
proper operation.
The MCP6566/6R/6U/7/9 family has internally-set
hysteresis
V
HYST
that is small enough to maintain input
offset accuracy and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage
E
NI
. Figure 4-1 depicts this behavior. Input
offset voltage (V
OS
) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (V
HYST
) is the difference between
the same trip points.
FIGURE 4-1: The MCP6566/6R/6U/7/9
comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltages that go too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-2: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the V
IN
+ and V
IN
– pins (see
Section 1.1 “Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V
IN
+ and V
IN
–) from going too far below ground, and
the resistors R
1
and R
2
limit the possible current drawn
out of the input pin. Diodes D
1
and D
2
prevent the input
pin (V
IN
+ and V
IN
–) from going too far above V
DD
.
When implemented as shown, resistors R
1
and R
2
also
limit the current through D
1
and D
2
.
FIGURE 4-3: Protecting the Analog
Inputs.
-3
-2
-1
0
1
2
3
4
5
6
7
8
Time (100 ms/div)
Output Voltage (V)
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
Input Voltage (10 mV/div)
V
OUT
V
IN
–
V
DD
= 5.0V
Hysteresis
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
R
1
V
DD
D
1
R
2

V
SS
– (minimum expected V
2
)
2mA
V
OUT
V
2
R
2
R
3
D
2
+
–
R
1

V
SS
– (minimum expected V
1
)
2mA
V
PU
R
4
MCP656X