Datasheet
MCP651/1S/2/3/4/5/9
DS22146C-page 28 2009-2011 Microchip Technology Inc.
FIGURE 4-11: Amplifier with Parasitic
Capacitance.
C
G
acts in parallel with R
G
(except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
C
G
also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing C
G
or R
F
.
C
N
and R
N
form a low-pass filter that affects the signal
at V
P
. This filter has a single real pole at 1/(2R
N
C
N
).
The largest value of R
F
that should be used depends
on noise gain (see G
N
in Section 4.4.1 “Capacitive
Loads”) and C
G
. Figure 4-12 shows the maximum
recommended R
F
for several C
G
values.
FIGURE 4-12: Maximum Recommended
R
F
vs. Gain.
Figure 2-37 and Figure 2-38 show the small signal and
large signal step responses at G = +1 V/V. The unity
gain buffer usually has R
F
=0 and R
G
open.
Figure 2-39 and Figure 2-40 show the small signal and
large signal step responses at G = -1 V/V. Since the
noise gain is 2 V/V and C
G
10 pF, the resistors were
chosen to be R
F
=R
G
=499 and R
N
= 249.
It is also possible to add a capacitor (C
F
) in parallel with
R
F
to compensate for the de-stabilizing effect of C
G
.
This makes it possible to use larger values of R
F
. The
conditions for stability are summarized in
Equation 4-10.
EQUATION 4-10:
4.5 Power Supply
With this family of operational amplifiers, the power
supply pin (V
DD
for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
4.6 High Speed PCB Layout
These op amps are fast enough that a little extra care
in the PCB (Printed Circuit Board) layout can make a
significant difference in performance. Good PC board
layout techniques will help you achieve the
performance shown in the specifications and Typical
Performance Curves; it will also help you minimize
EMC (Electro-Magnetic Compatibility) issues.
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low speed from high
speed, and low power from high power. This will reduce
interference.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect guard traces
to ground plane at both ends, and in the middle for long
traces.
Use coax cables, or low inductance wiring, to route
signal and power to and from the PCB. Mutual and self
inductance of power wires is often a cause of crosstalk
and unusual behavior.
V
P
R
F
V
OUT
MCP65X
R
N
C
N
V
M
R
G
C
G
1.E+02
1.E+03
1.E+04
1.E+05
1 10 100
Noise Gain; G
N
(V/V)
Maximum Recommended R
F
(Ω)
G
N
> +1 V/V
100
10k
100k
1k
C
G
= 10 pF
C
G
= 32 pF
C
G
= 100 pF
C
G
= 320 pF
C
G
= 1 nF
f
F
f
GBWP
2G
N2
, G
N1
G
N2
<
We need:
G
N1
1R
F
R
G
+=
G
N2
1C
G
C
F
+=
f
F
12
R
F
C
F
=
f
Z
f
F
G
N1
G
N2
=
Given:
f
F
f
GBWP
4G
N1
, G
N1
G
N2
>