Datasheet

 2009-2011 Microchip Technology Inc. DS22146C-page 25
MCP651/1S/2/3/4/5/9
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
mode voltage (V
CM
) is below ground (V
SS
); see
Figure 2-15. Applications that are high-impedance may
need to limit the usable voltage range.
4.2.3 NORMAL OPERATION
The input stage of the MCP651/1S/2/3/4/5/9 op amps
uses a differential PMOS input stage. It operates at low
Common mode input voltage (V
CM
), with V
CM
up to
V
DD
– 1.3V and down to V
SS
– 0.3V. The input offset
voltage (V
OS
) is measured at V
CM
=V
SS
–0.3V and
V
DD
– 1.3V to ensure proper operation. See Figure 2-6
and Figure 2-7 for temperature effects.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the V
CM
range
(< V
DD
–1.3V); see Figure 4-5
FIGURE 4-5: Unity Gain Voltage
Limitations for Linear Operation.
4.3 Rail-to-Rail Output
4.3.0.1 Maximum Output Voltage
The Maximum Output Voltage (see Figure 2-16 and
Figure 2-17) describes the output range for a given
load. For instance, the output voltage swings to within
15 mV of the negative rail with a 1 k load tied to
V
DD
/2.
4.3.0.2 Output Current
Figure 4-6 shows the possible combinations of output
voltage (V
OUT
) and output current (I
OUT
). I
OUT
is
positive when it flows out of the op amp into the
external circuit.
FIGURE 4-6: Output Current.
V
IN
MCP65X
V
DD
V
OUT
V
SS
V
IN
V
OUT
V
DD
1.3V–
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-120 -100
-80 -60 -40 -20
0
20 40 60 80
100 120
I
OUT
(mA)
V
OUT
(V)
R
L
= 10Ω
R
L
= 100ΩR
L
= 1 kΩ
V
OH
Limited
V
OL
Limited
-I
SC
Limited
+I
SC
Limited
(V
DD
= 5.5V)