Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsLinear ICsLinear IC - Op-amp Multi-purpose SOT 23 5

 2009-2011 Microchip Technology Inc. DS22146C-page 1

MCP651/1S/2/3/4/5/9

Features:

• Gain Bandwidth Product: 50 MHz (typical)

• Short Circuit Current: 100 mA (typical)

• Noise: 7.5 nV/Hz (typical, at 1 MHz)

• Calibrated Input Offset: ±200 µV (maximum)

• Rail-to-Rail Output

• Slew Rate: 30 V/µs (typical)

• Supply Current: 6.0 mA (typical)

• Power Supply: 2.5V to 5.5V

• Extended Temperature Range: -40°C to +125°C

Typical Applications:

• Driving A/D Converters

• Power Amplifier Control Loops

• Barcode Scanners

• Optical Detector Amplifier

Design Aids:

• SPICE Macro Models

•FilterLab

Software

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Description:

The Microchip Technology, Inc. MCP651/1S/2/3/4/5/9

family of operational amplifiers features low offset. At

power-up, these op amps are self-calibrated using

mCal. Some package options also provide a

calibration/chip select pin (CAL/CS

) that supports a

Low-Power mode of operation, with offset calibration at

the time normal operation is re-started. These

amplifiers are optimized for high speed, low noise and

distortion, single-supply operation with rail-to-rail

output and an input that includes the negative rail.

This family is offered in single (MCP651 and

MCP651S), single with CAL/CS

pin (MCP653), dual

(MCP652), dual with CAL/CS

pins (MCP655), quad

(MCP654) and quad with CAL/CS

pins (MCP659). All

devices are fully specified from -40°C to +125°C.

Typical Application Circuit

PowerDriverwithHighGain

MCP65X

OUT

50 MHz, 6 mA Op Amps with mCal

Summary of content (66 pages)

PAGE 1
MCP651/1S/2/3/4/5/9 50 MHz, 6 mA Op Amps with mCal Features: Description: • • • • • • • • • The Microchip Technology, Inc. MCP651/1S/2/3/4/5/9 family of operational amplifiers features low offset. At power-up, these op amps are self-calibrated using mCal. Some package options also provide a calibration/chip select pin (CAL/CS) that supports a Low-Power mode of operation, with offset calibration at the time normal operation is re-started.
PAGE 2
MCP651/1S/2/3/4/5/9 Package Types MCP651 2x3 TDFN * MCP651 SOIC NC 1 8 CAL/CS NC 1 VIN– 2 7 VDD VIN– 2 VIN+ 3 6 VOUT VIN+ 3 VSS 4 5 VCAL VSS 4 8 CAL/CS EP 9 MCP654 SOIC, TSSOP MCP651S SOT-23-5 7 VDD VSS 6 VOUT 5 VDD VOUT 1 2 VIN+ 3 5 VCAL 4 VIN– VOUTA 1 14 VOUTD VINA- 2 VINA+ 3 VDD 4 13 VIND- VINB+ 5 VINB- 6 10 VINC+ 12 VIND+ 11 VSS 9 VINC- VOUTB 7 5 VINB+ VSS 4 6 VINB– 5 VINB+ MCP655 3x3 DFN * VOUTA 1 VINA– 2 VINA+ 3 VSS 4 CALA/CSA 5 EP 11 VSS 5 CAL/CS 2 VIN+ 3 MCP6
PAGE 3
MCP651/1S/2/3/4/5/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. VDD – VSS .......................
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MCP651/1S/2/3/4/5/9 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL and CAL/CS = VSS (refer to Figure 1-2). Parameters Sym Min Typ Max Units mV Conditions Calibration Input VCALRNG VSS + 0.1 — VDD – 1.4 Internal Calibration Voltage VCAL 0.31VDD 0.33VDD 0.35VDD Input Impedance ZCAL — 100 || 5 — VDD 2.5 — 5.
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MCP651/1S/2/3/4/5/9 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL, CL = 20 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2). Parameters Sym Min Typ Max Units Conditions CAL/CS Logic Threshold, Low VIL VSS — 0.2VDD V CAL/CS Input Current, Low ICSL — 0 — nA CAL/CS Logic Threshold, High VIH 0.
PAGE 6
MCP651/1S/2/3/4/5/9 TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Conditions Temperature Ranges Specified Temperature Range (Note 1) Thermal Package Resistances Thermal Resistance, 5L-2×3 SOT JA — 220.
PAGE 7
MCP651/1S/2/3/4/5/9 1.4 Test Circuits The circuit used for most DC and AC tests is shown in Figure 1-2. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit’s Common mode voltage ((VP + VM)/2), and that VOST includes VOS plus the effects (on the input offset error, VOST) of temperature, CMRR, PSRR and AOL. CF 6.
PAGE 8
MCP651/1S/2/3/4/5/9 NOTES: DS22146C-page 8  2009-2011 Microchip Technology Inc.
PAGE 9
MCP651/1S/2/3/4/5/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 10
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS. 1 Lot High (VDD – VCMR_H) CMRR, PSRR (dB) High Input Common Mode Headroom (V) 1.4 1.3 VDD = 2.5V 1.2 1.1 VDD = 5.5V 1.0 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 CMRR, VDD = 5.5V CMRR, VDD = 2.5V -50 -25 120 115 VDD = 2.
PAGE 11
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, 160 140 120 100 80 60 40 20 0 -20 -40 -60 1.E-03 1m TA = +85°C VDD = 5.5V 100µ 1.E-04 10µ 1.E-05 IB 1µ 1.E-06 100n 1.E-07 10n 1.E-08 IOS 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C.
PAGE 12
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS. Other DC Voltages and Currents 14 8 VDD = 5.5V 12 7 VOL – VSS -IOUT 10 Supply Current (mA/amplifier) 8 6 4 VDD – VOH IOUT VDD = 2.5V 2 2 RL = 1 kΩ 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 FIGURE 2-19: Supply Voltage. Supply Current vs. Power 9 VOL – VSS 8 8 6 VDD – VOH VDD = 2.5V 1.
PAGE 13
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, 25% 144 Samples VDD = 2.5V and 5.5V 20% 15% 10% 5% Normalized Internal Calibration Voltage; VCAL/VDD FIGURE 2-22: Normalized Internal Calibration Voltage.  2009-2011 Microchip Technology Inc. 33.52% 33.48% 33.44% 33.40% 33.36% 33.32% 33.28% 33.24% 0% Internal V CAL Resistance (kΩ) 30% 33.
PAGE 14
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS. Frequency Response 0 100 -30 80 -60 AOL -90 -120 | AOL | 20 -150 0 -180 -20 -210 50 40 40 50 30 40 20 30 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 10 125 FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.
PAGE 15
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, 10 9 8 7 6 5 G = 1 V/V G = 2 V/V 4 G 4 V/V 3 2 1 0 10p 100p 1.0E-10 1n 10n 1.0E-11 1.0E-09 Normalized Capacitive Load; CL/G (F) FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load.  2009-2011 Microchip Technology Inc. Channel-to-Channel Separation (dB) Gain Peaking (dB) VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS.
PAGE 16
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS. Input Noise and Distortion 1.E+4 10μ Input Offset + Noise; VOS + e ni(t) (µV) 20 1.E+3 1μ 1.E+2 100n 1.E+1 10n 15 Representative Part NPBW = 0.1 Hz 10 5 0 -5 -10 -15 -20 1n 1.E+0 0.1 1.E-1 1 1.E+0 10 1.E+1 160 Input Noise Voltage Density THD + Noise (%) 100 VDD = 5.
PAGE 17
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS. 2.5 Time Response VIN 0 Output Voltage (V) Output Voltage (10 mV/div) VDD = 5.5V G=1 VOUT 20 40 60 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 80 100 120 140 160 180 200 Time (ns) Non-inverting Small Signal VIN VOUT 100 200 FIGURE 2-40: Response.
PAGE 18
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS. Maximum Output Voltage Swing (VP-P) 10 VDD = 5.5V VDD = 2.5V 1 0.1 100k 1.E+05 1M 10M 1.E+06 1.E+07 Frequency (Hz) 100M 1.E+08 FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency. DS22146C-page 18  2009-2011 Microchip Technology Inc.
PAGE 19
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS. Calibration and Chip Select Response 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.40 CAL/CS = VDD CAL/CS Hysteresis (V) CAL/CS Current (µA) 2.6 0.35 0.30 0.20 0.10 0.05 0.
PAGE 20
MCP651/1S/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS. 1.E-06 CAL/CS = VDD -1 Output Leakage Current (A) Negative Power Supply Current; ISS (µA) 0 -2 -3 -4 +125°C +85°C +25°C -40°C -5 -6 Power Supply Voltage (V) FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage. DS22146C-page 20 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.
PAGE 21
MCP651/1S/2/3/4/5/9 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1.
PAGE 22
MCP651/1S/2/3/4/5/9 3.1 Analog Outputs The analog output pins (VOUT) are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs (VIN+, VIN–, …) are high-impedance CMOS inputs with low bias currents. 3.3 Power Supply Pins The positive power supply (VDD) is 2.5V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration.
PAGE 23
MCP651/1S/2/3/4/5/9 4.0 APPLICATIONS The MCP651/1S/2/3/4/5/9 family of self-zeroed op amps is manufactured using Microchip’s state-of-the-art CMOS process. It is designed for low-cost, low-power and high precision applications. Its low supply voltage, low quiescent current and wide bandwidth makes the MCP651/1S/2/3/4/5/9 ideal for battery-powered applications. 4.1 Calibration and Chip Select These op amps include circuitry for dynamic calibration of the offset voltage (VOS). 4.1.
PAGE 24
MCP651/1S/2/3/4/5/9 When the VCAL pin is left open, the internal resistor divider generates a VCM_INT of approximately VDD/3, which is near the center of the input Common mode voltage range. It is recommended that an external capacitor from VCAL to ground be added to improve noise immunity. When the VCAL pin is driven by an external voltage source, which is within its specified range, the op amp will have its input offset voltage calibrated at that Common mode input voltage.
PAGE 25
When operating at very low non-inverting gains, the output voltage is limited at the top by the VCM range (< VDD – 1.3V); see Figure 4-5 +I SC Limited RL = 100Ω RL = 10Ω FIGURE 4-6: 120 80 100 60 40 20 0 -20 -40 -60 VOL Limited -80 The input stage of the MCP651/1S/2/3/4/5/9 op amps uses a differential PMOS input stage. It operates at low Common mode input voltage (VCM), with VCM up to VDD – 1.3V and down to VSS – 0.3V. The input offset voltage (VOS) is measured at VCM = VSS – 0.
PAGE 26
MCP651/1S/2/3/4/5/9 4.3.0.3 Power Dissipation Since the output short circuit current (ISC) is specified at ±100 mA (typical), these op amps are capable of both delivering and dissipating significant power. Two common loads, and their impact on the op amp’s power dissipation, will be discussed. Figure 4-7 shows a capacitive load (CL), which is driven by a sine wave with DC offset. The capacitive load causes the op amp to output higher currents at higher frequencies.
PAGE 27
MCP651/1S/2/3/4/5/9 EQUATION 4-7: n PPKG =  POA k=1 Where: n = Number of op amps in package (1 or 2) When driving large capacitive loads with these op amps (e.g., > 20 pF when G = +1), a small series resistor at the output (RISO in Figure 4-9) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load.
PAGE 28
MCP651/1S/2/3/4/5/9 EQUATION 4-10: RN VP Given: G N1 = 1 + R F  R G CN MCP65X G N2 = 1 + C G  C F VOUT VM RG FIGURE 4-11: Capacitance. CG f F = 1   2  RF C F  f Z = f F  G N1  G N2  We need: f F  fGBWP   2G N2  , G N1 < GN2 RF f F  fGBWP   4G N1  , G N1 > GN2 Amplifier with Parasitic CG acts in parallel with RG (except for a gain of +1 V/V), which causes an increase in gain at high frequencies. CG also reduces the phase margin of the feedback loop, which becomes less stable.
PAGE 29
MCP651/1S/2/3/4/5/9 4.7 Typical Applications 4.7.1 4.7.3 POWER DRIVER WITH HIGH GAIN Figure 4-13 shows a power driver with high gain (1 + R2/R1). The MCP651/1S/2/3/4/5/9 op amp’s short circuit current makes it possible to drive significant loads. The calibrated input offset voltage supports accurate response at high gains. R3 should be small, and equal to R1||R2, in order to minimize the bias current induced offset.
PAGE 30
MCP651/1S/2/3/4/5/9 NOTES: DS22146C-page 30  2009-2011 Microchip Technology Inc.
PAGE 31
MCP651/1S/2/3/4/5/9 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP651/1S/2/3/4/5/9 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP651/1S/2/3/4/5/9 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities.
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MCP651/1S/2/3/4/5/9 NOTES: DS22146C-page 32  2009-2011 Microchip Technology Inc.
PAGE 33
MCP651/1S/2/3/4/5/9 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SOT-23 (2x3) (MCP651S) XXNN YW25 6-Lead SOT-23 (2x3) (MCP653) Example: XXNN JD25 Example: 8-Lead TDFN(2x3) (MCP651) AAZ 124 25 Example: 8-Lead DFN (3x3) (MCP652) Device XXXX YYWW NNN Legend: XX...
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MCP651/1S/2/3/4/5/9 6.
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MCP651/1S/2/3/4/5/9 .
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 36  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 6 Pitch e 0.95 BSC Outside Lead Pitch e1 1.90 BSC Overall Height A 0.90 Molded Package Thickness A2 0.89 1.45 1.
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MCP651/1S/2/3/4/5/9 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 38  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 40  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 42  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 ! "# $%& ' * +, . # # $ # / ## +22--- 2 DS22146C-page 44 ! - / 0 # 1 / % # # ! #  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 46  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 . / # 0 1 4 ! 5 5&$7 ' * ./ . # # $ # / ## +22--- 2  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 48  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 50  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 8& 4 0 1 9 4 .
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MCP651/1S/2/3/4/5/9 10-Lead Plastic Micro Small Outline Package (UN) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 52  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 54  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 . # # $ # / ## +22--- 2  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 56  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 58  2009-2011 Microchip Technology Inc.
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MCP651/1S/2/3/4/5/9 8; < / # 0 1 4 ! =5=5&$% ' *
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MCP651/1S/2/3/4/5/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22146C-page 60  2009-2011 Microchip Technology Inc.
PAGE 61
MCP651/2/3/4/5/9 APPENDIX A: REVISION HISTORY Revision C (June 2011) The following is a list of modifications: 1. Added the 2x3 TDFN (8L) package option for MCP651, SOT-23 (5L) package for MCP651S and SOT-23 (6L) package option for MCP653 and the related information throughout the document. Revision B (March 2011) The following is a list of modifications: 1. 2. Added the MCP654 and MCP659 amplifiers to the product family and the related information throughout the document.
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MCP651/2/3/4/5/9 NOTES: DS22146C-page 62  2009-2011 Microchip Technology Inc.
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MCP651/2/3/4/5/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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MCP651/2/3/4/5/9 NOTES: DS22146B-page 64  2011 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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