Datasheet

MCP6481/2/4
DS20002322C-page 16  2012-2013 Microchip Technology Inc.
4.1.4 NORMAL OPERATION
The inputs of the MCP6481/2/4 op amps use two
differential input stages in parallel. One operates at a
low Common mode input voltage (V
CM
), while the other
operates at a high V
CM
. With this topology, the device
operates with a V
CM
up to 0.3V above V
DD
and 0.3V
below V
SS
(refer to Figures 2-3 and 2-4). The input
offset voltage is measured at V
CM
=V
SS
–0.3V and
V
DD
+ 0.3V to ensure proper operation.
The transition between the input stages occurs when
V
CM
is near V
DD
– 1.2V (refer to Figures 2-3 and 2-4).
For the best distortion performance and gain linearity,
with non-inverting gains, avoid this region of operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6481/2/4 op amps
is 0.007V (typical) and 5.493V (typical) when
R
L
=10k is connected to V
DD
/2 and V
DD
=5.5V.
Refer to Figures 2-23 and 2-24 for more information.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1V/V) is the
most sensitive to capacitive loads, all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = + 1V/V), a small series
resistor at the output (R
ISO
in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitance load.
FIGURE 4-4: Output Resistor, R
ISO
Stabilizes Large Capacitive Loads.
Figure 4-5 gives the recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit’s noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1 + |Signal Gain| (e.g., -1V/V gives G
N
=+2V/V).
After selecting R
ISO
for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6481/2/4 SPICE macro
model are helpful.
FIGURE 4-5: Recommended R
ISO
Values
for Capacitive Loads.
4.4 Supply Bypass
With this family of operational amplifiers, the power
supply pin (V
DD
for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor can be shared
with other analog parts.
V
IN
R
ISO
V
OUT
C
L
–
+
MCP648X
10
100
1000
o
mmended R
ISO
(:)
G
N
:
1 V/V
2 V/V
t
5V/V
V
DD
= 5.5 V
R
L
= 10 kȍ
1
1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Rec
o
Normalized Load Capacitance; C
L
/G
N
(F)
t
5
V/V
10p 100p 1n 10n 0.1µ 1µ