Datasheet

MCP6441/2/4
DS22257C-page 14 © 2010-2012 Microchip Technology Inc.
4.1.4 NORMAL OPERATION
The input stage of the MCP6441/2/4 op amp uses two
differential input stages in parallel. One operates at a
low Common Mode input voltage (V
CM
), while the other
operates at a high V
CM
. With this topology, the device
operates with a V
CM
up to 300 mV above V
DD
and
300 mV below V
SS
. The input offset voltage is
measured at V
CM
=V
SS
– 0.3V and V
DD
+ 0.3V, to
ensure proper operation.
The transition between the input stages occurs when
V
CM
is near V
DD
–0.6V (see Figures 2-3 and 2-4). For
the best distortion performance and gain linearity, with
non-inverting gains, avoid this region of operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6441/2/4 op amp
is V
SS
+ 20 mV (minimum) and V
DD
– 20 mV (maxi-
mum) when R
L
=10kΩ is connected to V
DD
/2 and
V
DD
= 6.0V. Refer to Figures 2-22 and 2-23 for more
information.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1 V/V) is the
most sensitive to the capacitive loads, all gains show
the same general behavior.
When driving large capacitive loads with the
MCP6441/2/4 op amp (e.g., > 100 pF when
G = +1 V/V), a small series resistor at the output (R
ISO
in Figure 4-4) improves the feedback loop’s phase mar-
gin (stability) by making the output load resistive at
higher frequencies. The bandwidth will be generally
lower than the bandwidth with no capacitance load.
FIGURE 4-4: Output Resistor, R
ISO
Stabilizes Large Capacitive Loads.
Figure 4-5 gives the recommended R
ISO
values for the
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit's noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
FIGURE 4-5: Recommended R
ISO
Values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6441/2/4 SPICE macro
model are very helpful.
4.4 Supply Bypass
The MCP6441/2/4 op amp’s power supply pin (V
DD
for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high
frequency performance. It can use a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other analog parts.
4.5 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
12
Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6441/2/4 op amp’s bias current at +25°C (±1 pA,
typical).
V
IN
R
ISO
V
OUT
C
L
–
+
MCP644X
1000
10000
100000
1000000
1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Normalized Load Capacitance; C
L
/G
N
(F)
Recommended R
ISO
(Ω)
G
N
:
1 V/V
2 V/V
≥
5 V/V
10p 100p 1n 10n 0.1µ 1µ
1k
10k
100k
1M